# US 5,706,322 A · Precision time of day counter

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- Number: US 5,706,322 A
- Document ID: US5706322A
- Status: Granted
- Kind: A
- Application number: 08/439,186
- Filed: 1995-05-11
- Granted: 1998-01-06
- Earliest claimed: 1995-05-11
- Assignees: E-Systems, Inc.
- Inventors: Albert D. Scalo; Bruce F. Karaffa
- Web page: https://patentgrep.com/patent/US5706322A

## CPC

- G04G 3/02: Circuits for deriving low frequency timing pulses from pulses of higher frequency (pulse frequency dividers in general H03K23/00 - H03K29/00)
- H03K 21/16: Circuits for carrying over pulses between successive decades
- H03K 23/50: using bi-stable regenerative trigger circuits (H03K23/42 - H03K23/48 take precedence)
- G04G: ELECTRONIC TIME-PIECES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A very high speed counter system of operating at frequencies of up to around 800 MHz provides timing measurements with accuracies on the order of (1/f) seconds where f is the frequency of operation. The least significant bit of the counter operates at the given frequency of a first clock signal while the other higher order bits operate at a second clock signal where the second clock signal is one-half the frequency of the first clock signal and is inverted. Carry lookahead circuits connected between stages of the second counter operate in conjunction with the clocking scheme to produce a high speed and accurate counter.

## Claims

### Claim 1

A counting system comprising:
a counter including a first stage having at least one register defining a bit position and a plurality of successive stages each having at least one register defining a bit position, said first stage responding to a first clock signal having periodic clock pulses of a first predetermined frequency and said successive stages responding to a second clock signal having periodic clock pulses of a second predetermined frequency, the second predetermined frequency having a different frequency value than the first predetermined frequency;
a circuit for generating lookahead carry signals applied to at least one of the successive stages of the counter; and
a clock input for supplying the first and second clock signals to the counter.

### Claim 2 (depends on 1)

A counting system in accordance with claim 1 wherein the frequency of the second clock signal is one-half the frequency of the first clock signal.

### Claim 3 (depends on 2)

A counting system in accordance with claim 2 wherein the clock input includes means for inverting the first clock signal and dividing the first clock signal by two to generate the second clock signal.

### Claim 4 (depends on 1)

A counting system in accordance with claim 1 wherein the frequency of the second clock signal is 1/(2.sup.b) of the frequency of the first clock signal where "b" equals the number of registers in the first stage.

### Claim 5 (depends on 1)

A counting system in accordance with claim 1 including a clock signal generator for generating the second clock signal 180 degrees out of phase with a most significant register of the first stage.

### Claim 6 (depends on 1)

A counting system in accordance with claim 1 wherein the first stage comprises one register and the plurality of successive stages further comprises:
a first successive stage having a plurality of registers each defining a bit position; and
a second successive stage having a plurality of registers each defining a bit position.

### Claim 7 (depends on 6)

A counting system in accordance with claim 6 wherein the first successive stage includes "n" registers defining bit positions B.sub.n through B.sub.1, and the circuit for generating lookahead carry signals comprises:
a first AND gate, the inputs to said first AND gate include the bits B.sub.n through B.sub.2 ;
a first NAND gate, the inputs to said first NAND gate include the output of the first AND gate and the inverse of bit B.sub.1 ;
a first carry flip-flop, the inputs to said first carry flip-flop include the second clock signal and the output from the first NAND gate;
an inverter for inverting the output of said first carry flipflop; and
a first connector for coupling the inverted output of said first carry flip-flop to the input of the second successive stage as a first carry signal.

### Claim 8 (depends on 7)

A counting system in accordance with claim 7 wherein the second successive stage includes "k" registers defining bit positions B.sub.k+n through B.sub.n+1, where "n" is the number of registers in the first successive stage, said plurality of successive stages further comprising a third successive stage having a plurality of registers each defining a bit position, and the circuit for generating lookahead carry signals further comprises:
a second AND gate, the inputs to said second AND gate include bits B.sub.k+n through B.sub.n+1 ;
an inverter for inverting the output of the second AND gate;
a first NOR gate, the inputs to said first NOR gate include the inverted output of the second AND gate and the output of the first carry flip-flop; and
a second connector for coupling the output of said first NOR gate to the input of the third successive stage as a second carry signal.

### Claim 9 (depends on 8)

A counting system in accordance with claim 8 wherein the third successive stage includes "p" registers defining bits B.sub.p+k+n through B.sub.k+n+1, where "n" and "k" are the number of registers in the first successive stage and second successive stage, respectively, said plurality of successive stages further comprising a fourth successive stage having a plurality of registers each defining a bit position, and the circuit for generating lookahead carry signals further comprises:
a third AND gate, the inputs to said third AND gate include bits B.sub.p+k+n through B.sub.k+n+1 and the output of the first NOR gate; and
a third connector for coupling the output of said third AND gate to the input of the fourth successive stage as a third carry signal.

### Claim 10 (depends on 9)

A counting system in accordance with claim 9 wherein the number of registers "n" equals twelve, the number of registers "k" equals twelve, the number of registers "p" equals twelve, the number of registers in the fourth successive stage equals nine, and the frequency of the first clock signal is at least about 400 megahertz.

### Claim 11 (depends on 9)

A counting system in accordance with claim 9 wherein the counter is programmable to a predetermined rollover count.

### Claim 12 (depends on 6)

A counting system in accordance with claim 6 wherein the two least significant bit registers of each of the first and second successive stages are duplicated to reduce the loading on the outputs of the two least significant bit registers.

### Claim 13 (depends on 6)

A counting system in accordance with claim 6 wherein the counter is programmable to a predetermined rollover count.

### Claim 14

A counting system comprising:
a first register defining a least significant bit, said first register responding to a first clock signal having periodic clock pulses of a first predetermined frequency;
a plurality of successive counting stages each having at least one register, each of said registers defining a bit position, said plurality of successive stages responding to a second clock signal having periodic clock pulses of a second predetermined frequency, the second predetermined frequency having a different frequency value than the first predetermined frequency; and
a circuit for generating lookahead catty signals applied to each of the plurality of successive stages.

### Claim 15 (depends on 14)

A counting system in accordance with claim 14 wherein the frequency of the second clock signal is one-half the frequency of the first clock signal.

### Claim 16 (depends on 14)

A counting system in accordance with claim 14 including a clock signal generator for generating the second clock signal substantially 180 degrees out of phase with the least significant bit of the first counter.

### Claim 17 (depends on 14)

A counting system in accordance with claim 14 further comprising:
a timing channel comprising the first register, a first latch register, and a second latch register, said timing channel receiving a timing signal for latching the value of the first register into the first latch register and the values of the registers in the plurality of successive stages into the second latch register.

### Claim 18 (depends on 17)

The counting system in accordance with claim 17 further comprising a plurality of timing channels, each timing channel comprising a first register, a first latch register and a second latch register and each of said timing channels receiving a respective timing signal for latching the value of the respective first register into the respective first latch register and the values of the registers in the plurality of successive stages into the respective second latch register.

### Claim 19 (depends on 14)

The counting system in accordance with claim 14 wherein the plurality of successive counting stages comprises:
a first successive stage comprising a plurality of registers "n" defining bits B.sub.n through B;
a second successive stage comprising a plurality of registers "k" defining bits B.sub.k+n through B.sub.+1 ;
a third successive stage comprising a plurality of registers "p" defining bits B.sub.p+k+n through B.sub.k+n+1 ;
where "n", "k" and "p" equal the number of registers in the first successive stage, the second successive stage and the third successive stage, respectfully.

### Claim 20 (depends on 19)

The counting system in accordance with claim 19 wherein the circuit for generating lookahead carry signals comprises:
a first AND gate, the inputs to said first AND gate include the bits B.sub.n through B.sub.2 ;
a first NAND gate, the inputs to said first NAND gate include the output of the first AND gate and the inverse of bit B.sub.1 ; and
a first carry flip-flop, the inputs to said first carry flip-flop include the second clock signal and the output from the first NAND gate whereby the output of said first carry flip-flop is inverted and coupled to the second successive stage and input as a first carry signal.

### Claim 21 (depends on 20)

The counting system in accordance with claim 20 wherein the circuit for generating lookahead carry signals further comprises:
a second AND gate, the inputs to said second AND gate include bits B.sub.k+n through B.sub.n+1 ;
an inverter for inverting the output of the second AND gate; and
a first NOR gate, the inputs to said NOR gate include the inverted output of the second AND gate and the output of the first carry flip-flop whereby the output of said first NOR gate is coupled to the third successive stage input as a second carry signal.

### Claim 22 (depends on 21)

The counting system in accordance with claim 21 wherein the circuit for generating lookahead carry signals further comprises:
a third AND gate, the inputs to said third AND gate include bits B.sub.p+k+n through B.sub.k+n+1 and the output of the first NOR gate whereby the output of said third AND gate is coupled and input as a third carry signal to a fourth successive stage comprising a plurality of registers "r" defining bits B.sub.r+p+k+.sub.n through B.sub.p+k+n+.

### Claim 23 (depends on 22)

The counting system in accordance with claim 22 wherein the number of registers "n", "k" and "p" equals twelve and the number of registers "r" equals nine.

### Claim 24

A precision time of day counting system comprising:
a first stage comprising at least one register defining a bit, said first stage responding to a first clock signal having periodic pulses;
a second stage comprising a plurality of subordinate counters interconnected to receive a plurality of carry signals, each of said subordinate counters having at least one register defining a bit, said second stage responding to a second clock signal having periodic clock pulses;
at least one circuit for generating and supplying the carry signals to the subordinate counters;
a first latch register for latching the least significant bit of the first stage in response to a timing signal;
a second latch register for latching the bits of the second stage in response to the timing signal; and
a shift register for serially outputting the bits in the first and second latch register.

### Claim 25 (depends on 24)

A precision time of day counting system in accordance with claim 24 wherein the second clock signal is 180 degrees out of phase with the most significant bit of the first counter.

### Claim 26 (depends on 25)

A precision time of day counting system in accordance with claim 25 wherein the at least one circuit for generating and supplying the carry signals comprises a plurality of gates interconnected to reduce the propagation delay through the second counter to less than about (2/f) where f is the frequency of the first clock signal.

### Claim 27 (depends on 26)

A precision time of day counting system in accordance with claim 26 wherein the second stage comprises:
a first subordinate counter comprising "n" registers defining bits B.sub.n through B.sub.1 ;
a second subordinate counter comprising "k" registers, defining bits B.sub.k+n through B.sub.n+1 ;
a third subordinate counter comprising "p" registers, defining bits B.sub.p+k+n through B.sub.k+n+1 ;
a fourth subordinate counter comprising "r" register, defining bits B.sub.r+p+k+n through B.sub.p+k+n+1 ; and
the first stage comprising a register defining bit B.sub.0.

### Claim 28 (depends on 27)

A precision time of day counting system in accordance with claim 27 wherein the two least significant bit registers of each the first, second and third subordinate counters are duplicated to reduce loading on the outputs of the two least significant bit registers.

### Claim 29 (depends on 24)

A precision time of day counting system in accordance with claim 24 further comprising a plurality of first stages, first latch registers, second latch registers and shift registers.

### Claim 30 (depends on 29)

A precision time of day counting system in accordance with claim 29 wherein the second clock signal is substantially 180 degrees out of phase with a most significant bit of the first stage.

### Claim 31

A counting system comprising:
a plurality of stages each having at least one register defining a bit position, said stages responding to a clock signal having periodic pulses of a predetermined frequency;
a circuit for generating lookahead carry signals applied to at least one of the plurality of stages;
a latch register for latching the bits of each of the stages in response to the timing signals; and
a shift register for serially outputting the bits of the latch register.

### Claim 32 (depends on 31)

A counting system in accordance with claim 31 wherein the plurality of stages comprises:
a first stage having "n" registers defining bit positions B.sub.n through B.sub.1 ;
a second stage having "k" registers defining bit positions B.sub.k+n through B.sub.n+1 ;
and wherein the circuit for generating lookahead signals comprises:
a first AND gate, the inputs to said first AND gate include the bits B.sub.n through B.sub.2 ;
an inverter for inverting the output of the second AND gate;
a first NAND gate, the inputs to said first NAND gate include the output of the first AND gate and the inverse of bit B.sub.1 ;
a first carry flip-flop, the inputs to said first carry flip-flop include the clock signal and the output from the first NAND gate;
an inverter for inverting the output of said first carry flip-flop; and
a first connector for coupling the inverted output of said first carry flip-flop to the input of the second stage as a first carry signal.

### Claim 33 (depends on 32)

A counting system in accordance with claim 32 wherein the plurality of stages further comprises a third stage having "p" registers defining bits B.sub.p+k+n through B.sub.k+n+1 and wherein the circuit for generating lookahead carry signals further comprises:
a second AND gate, the inputs to said second AND gate include bits B.sub.k+n through B.sub.n+1 ; and
an inverter for inverting the output of the second AND gate;
a first NOR gate, the inputs to said first NOR gate include the inverted output of the second AND gate and the output of the first carry flip-flop; and
a second connector for coupling the output of said first NOR gate to the input of the third stage as a second carry signal.

### Claim 34 (depends on 33)

A counting system in accordance with claim 33 wherein the plurality of stages further comprises a fourth stage and wherein the circuit for generating lookahead carry signals further comprises:
a third AND gate, the inputs to said third AND gate include bits B.sub.p+k+n through B.sub.k+n+1 and the output of the first NOR gate; and
a third connector for coupling the output of said third AND gate to the input of the fourth stage as a third carry signal.