# US 5,706,296 A · Bi-directional scan design with memory and latching circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,706,296 A - Document ID: US5706296A - Status: Granted - Kind: A - Application number: 08/395,543 - Filed: 1995-02-28 - Granted: 1998-01-06 - Earliest claimed: 1995-02-28 - Assignees: Texas Instruments Incorporated - Inventors: Lee D. Whetsel - Web page: https://patentgrep.com/patent/US5706296A ## CPC - G01R 31/318541: {Scan latches or cell details} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A scan cell (51) for use at an input/output terminal includes memory circuitry (Mem 1) for storing test data from a test data path, and a latching circuit (S4, LOB; S6, LIB) connected to the memory circuitry for receiving and selectively latching the test data stored in the memory circuitry. The input/output terminal has an input buffer (IB) and an output buffer (3SOB) associated therewith, and the latching circuit includes one of the input buffer and the output buffer. ## Claims ### Claim 1 An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including one of said input buffer and said output buffer. ### Claim 2 An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said input buffer and said output buffer. ### Claim 3 An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said output buffer, and said latching circuit operable to resolve voltage contention at said externally accessible terminal. ### Claim 4 An electrical circuit, comprising: Functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; a test data path for providing test data; first memory circuitry coupled to said test data path for storing test data received from said test data path; a first latching circuit connected to said first memory circuitry for receiving and selectively latching test data stored in said first memory circuitry, said first latching circuit including said input buffer; second memory circuitry coupled to said test data path for storing test data received from said test data path; and a second latching circuit connected to said second memory circuitry for receiving and selectively latching test data stored in said second memory circuitry, said second latching circuit including said output buffer. ### Claim 5 An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; a terminal which is accessible externally of said electrical circuit; an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal; an input buffer having an input and an output, said input coupled to said externally accessible terminal for driving to said output signals received at said externally accessible terminal; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said input buffer and said output buffer. ### Claim 6 (depends on 5) The circuit of claim 5, wherein said latching circuit includes a feedback element connected between said output of said input buffer and an input of said output buffer. ### Claim 7 (depends on 6) The circuit of claim 6, wherein said feedback element is a transmission gate. ### Claim 8 (depends on 6) The circuit of claim 6, wherein said feedback element is a 2-state buffer. ### Claim 9 (depends on 6) The circuit of claim 6, wherein said feedback element is a 3-state buffer. ### Claim 10 (depends on 6) The circuit of claim 6, wherein said latching circuit includes a switch connected between said functional circuitry and said input of said output buffer. ### Claim 11 (depends on 10) The circuit of claim 10, wherein said switch is a transmission gate. ### Claim 12 (depends on 10) The circuit of claim 10, wherein said switch is a 3-state buffer. ### Claim 13 (depends on 2) The circuit of claim 2, wherein said latching circuit includes a feedback element connected between an output of said input buffer and an input of said output buffer. ### Claim 14 (depends on 13) The circuit of claim 13, wherein said feedback element is a transmission gate. ### Claim 15 (depends on 13) The circuit of claim 13, wherein said feedback element is a 2-state buffer. ### Claim 16 (depends on 13) The circuit of claim 13, wherein said feedback element is a 3-state buffer. ### Claim 17 (depends on 13) The circuit of claim 13, wherein said latching circuit includes a switch connected between said functional circuitry and said input of said output buffer. ### Claim 18 (depends on 17) The circuit of claim 17, wherein said switch is a transmission gate. ### Claim 19 (depends on 17) The circuit of claim 17, wherein said switch is a 3-state buffer.