# US 5,706,293 A · Method of testing single-order address memory

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- Number: US 5,706,293 A
- Document ID: US5706293A
- Status: Granted
- Kind: A
- Application number: 08/650,936
- Filed: 1996-05-17
- Granted: 1998-01-06
- Earliest claimed: 1995-05-18
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Heon-cheol Kim; Ho-ryong Kim; Sang-hyeon Baeg; Chang-hyun Cho
- Web page: https://patentgrep.com/patent/US5706293A

## CPC

- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present invention provides a test method of SOA (Single-Order Addressed) memory utilizing address data backgrounds applied to memory circuits. A memory test operation is performed using a total of (log.sub.2 N+1) address data backgrounds on an SOA memory having N mutually different addresses. Each address data background is written and read, then the inversion is written and read. Finally the address data background is again written and read for a total of 6 N(log.sub.2 N+1) operations.

## Claims

### Claim 1

A method of testing a single-order address memory having N memory cells and N mutually different addresses in the memory, said method comprising:
(a) creating a plurality of test vectors each having N bits of data, where M is the number of consecutive bits in each vector having the same state, including:
(1) defining a first vector in which each bit is 0;
(2) defining another vector in which the first M2 bits in each group of M bits in the previously defined vector is set to 0 and the second group of M2 bits in each group is set to 1; and
(3) repeating step (2) until log.sub.2 N+1 vectors are created;
(b) selecting one of the vectors;
(c) writing the selected vector into each memory cell, including:
writing the first bit of the selected vector into each location of a first one of said memory cells; and
writing each successive bit of the selected vector into each location of a different one of said memory cells;
(d) reading data stored at each address;
(e) writing the inversion of the selected vector into each memory cell, including:
writing the first bit of the inversion of the selected vector into each location of the first one of said memory cells; and
writing each successive bit of the inversion of the selected vector into each location of a different one of said memory cells;
(f) reading data stored at each address;
(g) writing the selected vector into each memory cell;
(h) reading data stored at each address; and
(i) performing steps (c) through (h) with each of the remaining test vectors.