# US 5,706,248 A · Data transfer system

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- Number: US 5,706,248 A
- Document ID: US5706248A
- Status: Granted
- Kind: A
- Application number: 08/751,023
- Filed: 1996-11-15
- Granted: 1998-01-06
- Earliest claimed: 1992-08-28
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Haruki Toda
- Web page: https://patentgrep.com/patent/US5706248A

## CPC

- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/103: {using serially addressed read-write data registers (G11C7/1036 takes precedence)}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A data transfer system, comprising: a plurality of data input/output gates arranged by k-unit group by k-unit group in a predetermined sequence; gate selecter circuit each arranged for k-unit group of the gates, for selecting the gates in unit of k-unit group; a plurality of data transfer paths for transferring data via the gates selected by the gate selecting means; a first register group composed of a-units of data registers for transferring data simultaneously to and from the data transfer paths, the a-unit data registers being serial-accessed in a constant sequence; and a scrambler circuit for designating any required data input/output gates and for further selectively connecting the data transfer paths connected to said designated data input/output gates with the data registers so that the data transfer paths connected to the designated input/output gates can be connected to the serial-accessible registers in a predetermined sequence, when the number of the data transfer paths is (L.times.k) under the following conditions: if a (mod k).ident.0, 1, L=›a/k!+1 if other than the above, L=›a/k!+2 where L denotes a maximum number of the gate selecting means selectable simultaneously.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a memory cell array (MCA) composed of a plurality of memory cells arranged into a matrix pattern and having n.about.pairs of bit lines, a plurality of the memory cells arranged in a column direction being connected to each of the bit line pairs;
a row decode circuit (RD) for decoding a row address inputted thereto to select the memory cells arranged in a row direction;
(2k)-units of data lines (DLN), number (2k) of said data lines being smaller than n, each of the bit line pairs being connected to any of said data lines and thereby a plurality of the bit line pairs being connected in common to each of said data lines;
n-units of column gates (11, 12, . . . ) each connected between each of said data lines and each of the bit line pairs and turned on or off to connect or disconnect each of said data lines to and from each of the bit line pairs;
n/k-units of column select lines (C1, C2, C3, C4, each connected to control terminals of mutually-adjacent k-units of said column gates, for turning on or off said k-unit column gates simultaneously; the first to fourth column select lines (C1 to C4) turning on first to k-th column gates, (k+1)-th to (2.times.k)-th column gates, (2.times.k+1)-th to (3.times.k)-th column gates, and (3.times.k+1)-th to (4.times.k)-th column gates, respectively to select the corresponding first to k-th, (k+1)-th to (2.times.k)-th, (2.times.k+1)-th to (3.times.k)-th, and (3.times.k+1)-th to (4.times.k)-th bit line pairs, respectively;
a column gate select circuit (CGS) for activating said column select lines;
a data buffer (4) connected to the said data lines, for buffering and outputting data read to said data lines;
register means (51, 52) having 2k-units of registers each for storing one-bit data outputted by said buffer;
a transfer circuit (61, 62) connected between said data buffer and said register means, for scrambling 2k-units of data outputted by said data buffer and storing the scrambled data in the registers of said register means in a predetermined sequence;
a scanning circuit (9) for scanning the registers in the predetermined sequence to output data stored in the registers;
an output buffer circuit (8) for buffering and outputting data given by said scanning circuit to the outside; and
in cyclic and continuous selection of the bit line pairs,
i) when the bit line pair to be selected first is selected by said column select line C1, said column gate select circuit selects said column select lines in sequence of (C1, C2), (C2, C3), (C3, C4), (C4, C1);
ii) when the bit line pair to be selected first is selected by said column select line C2, said column gate select circuit selects said column select lines in sequence of (C2, C1), (C1, C4), (C4, C3) (C3, C2);
iii) when the bit line pair to be selected first is selected by said column select line C3, said column gate select circuit selects said column select lines in sequence of (C3, C4), (C4, C1), (C1, C2), (C2, C3); and
iv) when the bit line pair to be selected first is selected by said column select line C4, said column gate select circuit selects said column select lines in sequence of (C4, C3), (C3, C2), (C2, C1), (C1, C4).

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein said register means is composed of t-units of register groups each composed of the k-unit registers, the respective register groups being interleaved in use.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein said transfer circuit is composed of t-units of transfer circuit units each connected between said data buffer and each of the register groups.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein said scanning circuit is activated on the basis of a clock signal.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, wherein k=2.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein k=3.