# US 5,706,246 A · Address transition detection circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,706,246 A - Document ID: US5706246A - Status: Granted - Kind: A - Application number: 08/734,268 - Filed: 1996-10-21 - Granted: 1998-01-06 - Earliest claimed: 1996-03-11 - Assignees: LG Semicon Co., Ltd. - Inventors: Kyun-Kyu Choi; Yong-Weon Jeon - Web page: https://patentgrep.com/patent/US5706246A ## CPC - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An address transition detection circuit for driving an internal circuit of a memory device, includes an address input circuit for generating an input logic operation signal by a logic operation of a chip select signal and an address signal, a latch circuit for generating first and second latch signals, a feedback circuit for generating a feedback signal, first and second delay circuits for generating first and second delay signals by delaying the first and second latch signals for a prescribed delay time, and an address transition detection signal output circuit for receiving the first and second latch signals and the first and second delay signals, and generating an address transition detection signal having a pulse width longer than at least the twice the prescribed delay time of the first or second delay circuit when the address signal changes, thereby preventing malfunction of the memory device. ## Claims ### Claim 1 An address transition detection circuit comprising: an address input circuit for generating an input logic operation signal by operating on a chip select signal and an address signal; a latch circuit for transferring said input logic operation signal and an inverted input logic operation signal to first input terminals of first and second NAND gates, respectively, and supplying first and second delay signals to second input terminals of said first and second NAND gates, so as to generate first and second latch signals; a feedback circuit for generating a second feedback signal, said second feedback signal transferring said input logic operation signals to the first input terminals of said first and second NAND gates when said first and second latch signals have an opposite phase; first and second delay circuits for generating said first and second delay signals by delaying said first and second latch signals for a prescribed delay time; and an address transition detection signal output circuit for receiving said first and second latch signals and said first and second delay signals, and generating an address transition detection signal having a pulse width longer than said prescribed delay time when said address signal is changed. ### Claim 2 (depends on 1) An address transition detection circuit as claimed in claim 1, wherein said latch circuit prevents said input logic operation signals from being transferred to said first and second NAND gates, when said first and second latch signals have the same phase. ### Claim 3 (depends on 1) An address transition detection circuit as claimed in claim 1, wherein said latch circuit includes: transistors for transferring said input logic operation signals to the first input terminals of said first and second NAND gates by said second feedback signal or for preventing said input logic operation signals from being transferred to said first and second NAND gates. ### Claim 4 (depends on 3) An address transition detection circuit as claimed in claim 3, wherein said transistors are NMOS transistors. ### Claim 5 (depends on 1) An address transition detection circuit as claimed in claim 1, wherein said latch circuit includes: voltage level adjusting means connected to the first input terminals of said first and second NAND gates, for adjusting a voltage level. ### Claim 6 (depends on 5) An address transition detection circuit as claimed in claim 5, wherein said voltage level adjusting means includes: an input terminal commonly connected to output terminals of said first and second NAND gates, and an output terminal connected to input terminals of said first and second NAND gates. ### Claim 7 (depends on 5) An address transition detection circuit as claimed in claim 5, wherein said voltage level adjusting means includes: a PMOS transistor and a first NMOS transistor of a CMOS transistor construction serially connected between a power voltage terminal and a ground voltage terminal. ### Claim 8 (depends on 7) An address transition detection circuit as claimed in claim 7, wherein said voltage level adjusting means further includes: a second NMOS transistor connected between said first NMOS transistor and said ground voltage terminal. ### Claim 9 (depends on 1) An address transition detection circuit as claimed in claim 1, wherein said feedback circuit includes: a fourth NAND gate for generating said second feedback signal, said fourth NAND gate having an input terminal connected to output terminals of said first and second NAND gates. ### Claim 10 (depends on 9) An address transition detection circuit as claimed in claim 9, wherein said feedback circuit further includes: a third NAND gate for transmitting a first feedback signal to said fourth NAND gate, said third NAND gate being connected to output terminals of said first and second delay circuits. ### Claim 11 (depends on 10) An address transition detection circuit as claimed in claim 10, wherein said first feedback signal is applied to a gate of said second NMOS transistor connected between said first NMOS transistor and said ground voltage terminal. ### Claim 12 (depends on 1) An address transition detection circuit as claimed in claim 1, wherein the address transition detection signal generated by said address transition detection signal output circuit has a pulse width longer than at least twice said prescribed delay time. ### Claim 13 An address transition detection circuit comprising: an address input circuit for generating an input logic operation signal by a logic operation of a chip select signal and an address signal having a given pulse width; a latch circuit for generating first and second latch signals, said latch circuit including first and second NAND gates having first input terminals to which said input logic operation signal and an inverted input logic operation signal are transferred, said latch circuit further including voltage adjusting means for adjusting a voltage of the first input terminals of said first and second NAND gates; a feedback circuit having a third NAND gate for generating a first feedback signal by said first and second delay signals, and having a fourth NAND gate for receiving said first feedback signal and said first and second latch signals and generating a second feedback signal; first and second delay circuits for generating said first and second delay signals by delaying said first and second latch signals for a prescribed delay time; and an address transition detection signal output circuit for receiving said first and second latch signals and said first and second delay signals, and generating an address transition detection signal having a pulse width longer than said prescribed delay time of said first or second delay circuit when said address signal is changed. ### Claim 14 (depends on 13) An address transition detection circuit as claimed in claim 13, wherein said voltage level adjusting means includes: a PMOS transistor and first and second NMOS transistors serially connected between a power voltage terminal and a ground voltage terminal. ### Claim 15 (depends on 14) An address transition detection circuit as claimed in claim 14, wherein said voltage level adjusting means includes: an input terminal commonly connected to output terminals of said first and second NAND gates, and an output terminal connected to input terminals of said first and second NAND gates, said second NMOS transistor having a gate connected to said third NAND gate. ### Claim 16 (depends on 13) An address transition detection circuit as claimed in claim 13, wherein said said second feedback signal transfers said input logic operation signals to the first input terminals of said first and second NAND gates when said first and second latch signals have an opposite phase, and prevents said input logic operation signals from being transferred to said first and second NAND gates when said first and second latch signals have the same phase. ### Claim 17 (depends on 13) An address transition detection circuit as claimed in claim 13, wherein the address transition detection signal generated by said address transition detection signal output circuit has a pulse width longer than at least twice said prescribed delay time. ### Claim 18 An address transition detection device comprising: an address input circuit for generating an input logic operation signal by operating on a chip select signal and an address signal having a pulse width; a latch circuit for receiving said input logic operation signal and an inverted input logic operation signal and generating first and second latch signals; a feedback circuit coupled to said latch circuit for generating first and second feedback signals and controlling said latch circuit; first and second delay circuits for generating first and second delay signals by delaying said first and second latch signals generated by said latch circuit for a prescribed delay time; and an address transition detection signal output circuit for receiving said first and second latch signals and said first and second delay signals, and generating an address transition detection signal having a pulse width longer than said prescribed delay time, irrespective of the pulse width of said address signal. ### Claim 19 (depends on 18) An address transition detection circuit device as claimed in claim 18, wherein said second feedback signal prevents said input logic operation signals from being transferred to first and second NAND gates of said latch circuit, when said first and second latch signals have the same phase. ### Claim 20 (depends on 19) An address transition detection circuit device as claimed in claim 19, wherein said latch circuit includes: transistors for transferring said input logic operation signals to first input terminals of said first and second NAND gates or for preventing said input logic operation signals from being transferred to said first and second NAND gates. ### Claim 21 (depends on 18) An address transition detection circuit device as claimed in claim 18, wherein said latch circuit includes: voltage level adjusting means connected to first and second NAND gates of said latch circuit, for adjusting a voltage level thereof. ### Claim 22 (depends on 21) An address transition detection circuit device as claimed in claim 21, wherein said voltage level adjusting means includes: an input terminal commonly connected to output terminals of said first and second NAND gates, and an output terminal connected to input terminals of said first and second NAND gates. ### Claim 23 (depends on 21) An address transition detection circuit device as claimed in claim 21, wherein said voltage level adjusting means includes: a PMOS transistor and a first NMOS transistor serially connected between a power voltage terminal and a ground voltage terminal. ### Claim 24 (depends on 23) An address transition detection circuit device as claimed in claim 23, wherein said voltage level adjusting means further includes: a second NMOS transistor connected between said first NMOS transistor and said ground voltage terminal. ### Claim 25 (depends on 20) An address transition detection circuit device as claimed in claim 20, wherein said feedback circuit includes: a fourth NAND gate for generating said second feedback signal, said fourth NAND gate having an input terminal connected to output terminals of said first and second NAND gates. ### Claim 26 (depends on 25) An address transition detection circuit device as claimed in claim 25, wherein said feedback circuit further includes: a third NAND gate for transmitting said first feedback signal to said fourth NAND gate, said third NAND gate being connected to output terminals of said first and second delay circuits. ### Claim 27 (depends on 24) An address transition detection circuit device as claimed in claim 24, wherein said first feedback signal is applied to a gate of said second NMOS transistor connected between said first NMOS transistor and said ground voltage terminal. ### Claim 28 (depends on 18) An address transition detection circuit as claimed in claim 18, wherein the address transition detection signal generated by said address transition detection signal output circuit has a pulse width longer than at least twice said prescribed delay time. ### Claim 29 A method of detecting an address transition for a memory device, comprising the steps of: generating an input logic operation signal and an inverted input logic operation signal by operating on a chip select signal and an address signal; receiving said input logic operation signals and generating first and second latch signals using a latch circuit; generating first and second delay signals by delaying said first and second latch signals for a prescribed delay time; generating first and second feedback signals by using said first and second delay signals to control said latch circuit; and receiving said first and second latch signals and said first and second delay signals, and generating an address transition detection signal having a pulse width longer than said prescribed delay time, irrespective of the pulse width of said address signal. ### Claim 30 (depends on 29) A method as claimed in claim 29, wherein said second feedback signal prevents said input logic operation signals from being transferred to said latch circuit, when said first and second latch signals have the same phase. ### Claim 31 (depends on 29) A method as claimed in claim 29, wherein said step of generating said first and second latch signals includes the step of: transferring said input logic operation signals to first input terminals of first and second NAND gates in said latch circuit. ### Claim 32 (depends on 29) A method as claimed in claim 29, wherein the address transition detection signal has a pulse width longer than at least twice the prescribed delay time.