# US 5,706,243 A · Semiconductor memory and method of using the same, column decoder, and image processor

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- Number: US 5,706,243 A
- Document ID: US5706243A
- Status: Granted
- Kind: A
- Application number: 08/534,098
- Filed: 1995-09-26
- Granted: 1998-01-06
- Earliest claimed: 1994-09-27
- Assignees: Matsushita Electric Industrial Co., Ltd.
- Inventors: Toshiki Mori
- Web page: https://patentgrep.com/patent/US5706243A

## CPC

- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/1033: {using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode}
- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 8/14: Word line organisation; Word line lay-out
- G09G 5/39: Control of the bit-mapped memory
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

In a semiconductor memory for storing image data, memory cell blocks each containing a plurality of memory cells arranged in a column direction are formed such that the plurality of memory cells belonging to each of the memory cell blocks are connected with a sub word line. The above memory cell blocks are arranged in an array. There are installed a plurality of horizontal word lines and a plurality of diagonal word lines. By selecting one of the horizontal word lines, a set of rectangular-region data of the image data is stored in the respective memory cells of the plurality of memory cell blocks placed in a given column direction. By selecting one of the diagonal word lines, sets of rectangular-region data placed in the same column are read out. Consequently, by selecting one of the horizontal word lines or one of the diagonal word lines, either or both of a set of rectangular-region data and one line of data on an image can be accessed at a high speed using a page mode cycle.

## Claims

### Claim 1

A semiconductor memory comprising:
a memory cell array having a plurality of memory cell blocks in each of which a single or a plurality of memory cells arranged in a column direction are connected to a sub word line, said plurality of memory cell blocks being arranged in an array;
horizontal word lines extending in horizontal directions and diagonal word lines extending in diagonal directions; and
a word-line selecting means for receiving a word-line select signal, selecting a given one of said horizontal or diagonal word lines based on the word-line select signal which has been received, and connecting the selected word line to said sub word line in each of the memory cell blocks corresponding to the word line, wherein
those ones of said plurality of memory cell blocks which are arranged in one of the horizontal directions or in one of the diagonal directions are selected based on the word-line select signal and sets of data in the plurality of memory cells in the plurality of selected memory cell blocks arranged in the horizontal direction or in the diagonal direction are outputted onto respective pairs of bit lines.

### Claim 2 (depends on 1)

A semiconductor memory according to claim 1, wherein
the word-line selecting means comprises a word-line selecting circuit having an input connected to one of the horizontal word lines and one of the diagonal word lines and having an output connected to the corresponding sub word line, while receiving the word-line select signal, selecting either one of said horizontal word line and said diagonal word line based on the word-line select signal which has been received, and connecting the selected word line to said sub word line.

### Claim 3 (depends on 1)

A semiconductor memory according to claim 1, further comprising:
a serial access memory for receiving and storing a plurality of signals, said plurality of stored signals being sequentially accessed in accordance with a serial clock; and
a transfer means for transferring and inputting signals on the plurality of bit lines to said serial access memory.

### Claim 4 (depends on 1)

A method of using the semiconductor memory according to claim 1, wherein a large number of sets of data are stored in the memory cells of the semiconductor memory and the horizontal word lines extending in the horizontal directions and the diagonal word lines extending in the diagonal directions are provided, said method comprising the steps of:
sequentially storing, in the memory cells of the memory cell blocks arranged in a given column, a set of data in a rectangular region in which the number in a column direction of the memory cells constituting each of the memory cell blocks is used as a number in a column direction and the number in a row direction of the memory cell blocks is used as a number in a row direction, said step being repeatedly performed; and
in storing the set of data in said rectangular region, storing the set of data in the column corresponding to the rectangular region in the memory cell blocks selected by one of the diagonal word lines.

### Claim 5

An image processor comprising:
a semiconductor memory comprising a memory cell array having a plurality of memory cell blocks in each of which a single or a plurality of memory cells arranged in a column direction are connected to a sub word line, said plurality of memory cell blocks being arranged in an array, horizontal word lines extending in horizontal directions and diagonal word lines extending in diagonal directions, and a word-line selecting means for receiving a word-line select signal, selecting a given one of said horizontal or diagonal word lines based on the word-line select signal which has been received, and connecting the selected word line to said sub word line in each of the memory cell blocks corresponding to the word line, wherein those ones of said plurality of memory cell blocks which are arranged in one of the horizontal directions or in one of the diagonal directions are selected based on the word-line select signal and sets of data in the plurality of memory cells in the plurality of selected memory cell blocks arranged in the horizontal direction or in the diagonal direction are outputted onto a pair of bit lines;
a register file composed of a plurality of line registers for receiving and storing sets of data from the bit lines of said semiconductor memory; and
a parallel arithmetic unit having a plurality of arithmetic circuits each for fetching in parallel the sets of data stored in the line registers of said register file and performing an arithmetic operation using the sets of fetched data.

### Claim 6 (depends on 5)

An image processor according to claim 5, further comprising
a reading means for serially reading the set of data stored in one of the line registers of the register file.

### Claim 7 (depends on 5)

An image processor according to claim 5, further comprising
an inputting means for serially inputting the set of data to one of the line registers of the register file.