# US 5,706,241 A · Eeprom semiconductor memory device including circuit for generating a voltage higher than a power supply voltage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,706,241 A - Document ID: US5706241A - Status: Granted - Kind: A - Application number: 08/616,428 - Filed: 1996-03-15 - Granted: 1998-01-06 - Earliest claimed: 1995-03-15 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Hiroshi Nakamura; Toru Tanzawa - Web page: https://patentgrep.com/patent/US5706241A ## CPC - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/30: Power supply circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device comprising a memory cell array of a plurality of memory cells formed and arranged on either a semiconductor substrate or a well of a first conductivity type formed on said semiconductor substrate, a plurality of voltage generating circuits for applying said memory cells voltages that are higher than the power supply voltage and different from each other and a switching circuit for selectively connecting the output nodes of said plurality of voltage generating circuits. ## Claims ### Claim 1 A semiconductor memory device comprising: a semiconductor substrate; a memory cell array having a plurality of memory cells formed on one of said semiconductor substrate and a first conductive well formed on said semiconductor substrate; a plurality of voltage generating circuits for applying voltages to said plurality of memory cells, said voltages being higher than a power supply voltage and different from each other; and a switching circuit for connecting each of output nodes of said plurality of voltage generating circuits to said plurality of memory cells. ### Claim 2 (depends on 1) A semiconductor memory device according to claim 1, wherein each of said plurality of voltage generating circuits has a pump circuit and a voltage limiter circuit and the operation of all the voltage limiter circuits is stopped except a single voltage limiter circuit when the nodes are connected by said switching circuit. ### Claim 3 (depends on 2) A semiconductor memory device according to claim 2, wherein said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 4 (depends on 3) A semiconductor memory device according to claim 3, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 5 (depends on 1) A semiconductor memory device according to claim 1, wherein each of said plurality of voltage generating circuit has a pump circuit and a voltage limiter circuit, and said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 6 (depends on 5) A semiconductor memory device according to claim 5, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 7 (depends on 1) A semiconductor memory device according to claim 1, wherein said output nodes individually output different voltages in a case of a first operation which said plurality of output nodes are unconnected and output the same voltage in a case of a second operation which said plurality of output nodes are connected. ### Claim 8 (depends on 7) A semiconductor memory device according to claim 7, wherein each of said plurality of voltage generating circuits has a pump circuit and a voltage limiter circuit and the operation of all the voltage limiter circuits is stopped except a single voltage limiter circuit when the nodes are connected by said switching circuit. ### Claim 9 (depends on 8) A semiconductor memory device according to claim 8, wherein said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 10 (depends on 9) A semiconductor memory device according to claim 9, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 11 (depends on 7) A semiconductor memory device according to claim 7, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, and the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit. ### Claim 12 (depends on 7) A semiconductor memory device according to claim 7, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, operations of first and second voltage limiter circuits are suspended, first and second voltage generating circuits are connected in series by said exchange circuit, and the output nodes of the series circuit and third voltage generating circuit are connected. ### Claim 13 (depends on 7) A semiconductor memory device according to claim 7, wherein said second operation is an operation of data erase operation. ### Claim 14 A semiconductor memory device comprising: a memory cell array of a plurality of memory cells formed and arranged on a semiconductor substrate; a first voltage generating circuit for applying a first voltage V.sub.1 higher than the power supply voltage to said memory cells; a second voltage generating circuit for applying a second voltage V.sub.2 higher than the power supply voltage to said memory cells; a third voltage generating circuit for applying a third voltage V.sub.3 higher than the power supply voltage to said memory cells; and a exchange circuit for connecting said first and second voltage generating circuits in series and the output of said series circuit to the output node of said third voltage generating circuit. ### Claim 15 (depends on 14) A semiconductor memory device according to claim 14, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, and the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit. ### Claim 16 (depends on 14) A semiconductor memory device according to claim 14, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit, and operations of first and second voltage limiter circuits are suspended. ### Claim 17 (depends on 16) A semiconductor memory device according to claim 16, wherein each of said plurality of voltage generating circuits has a pump circuit and a voltage limiter circuit and the operation of all the voltage limiter circuits is stopped except a single voltage limiter circuit when the nodes are connected by said switching circuit. ### Claim 18 (depends on 17) A semiconductor memory device according to claim 17, wherein said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 19 (depends on 18) A semiconductor memory device according to claim 18, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 20 (depends on 14) A semiconductor memory device according to claim 14, wherein said output nodes individually output different voltages in a case of a first operation which said plurality of output nodes are unconnected and output the same voltage in a case of a second operation which said plurality of output nodes are connected. ### Claim 21 (depends on 20) A semiconductor memory device according to claim 20, wherein each of said plurality of voltage generating circuits has a pump circuit and a voltage limiter circuit and the operation of all the voltage limiter circuits is stopped except a single voltage limiter circuit when the nodes are connected by said switching circuit. ### Claim 22 (depends on 21) A semiconductor memory device according to claim 21, wherein said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 23 (depends on 22) A semiconductor memory device according to claim 22, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 24 (depends on 20) A semiconductor memory device according to claim 20, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, and the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit. ### Claim 25 (depends on 20) A semiconductor memory device according to claim 20, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit, and operations of first and second voltage limiter circuits are suspended. ### Claim 26 (depends on 20) A semiconductor memory device according to claim 20, wherein said second operation is an operation of data erase operation. ### Claim 27 (depends on 1) A semiconductor memory device according to claim 1, wherein in a case of one of connecting and unconnecting said output nodes of said plurality of voltage generating circuit, at least one of said plurality of voltage generating circuit changes in structure. ### Claim 28 (depends on 27) A semiconductor memory device according to claim 27, wherein each of said plurality of voltage generating circuits has a pump circuit and a voltage limiter circuit and the operation of all the voltage limiter circuits is stopped except a single voltage limiter circuit when the nodes are connected by said switching circuit. ### Claim 29 (depends on 28) A semiconductor memory device according to claim 28, wherein said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 30 (depends on 29) A semiconductor memory device according to claim 29, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 31 (depends on 27) A semiconductor memory device according to claim 27, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, and the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit. ### Claim 32 (depends on 27) A semiconductor memory device according to claim 27, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit, and operations of first and second voltage limiter circuits are suspended. ### Claim 33 (depends on 27) A semiconductor memory device according to claim 27, wherein said output nodes individually output different voltages in a case of a first operation which said plurality of output nodes are unconnected and output the same voltage in a case of a second operation which said plurality of output nodes are connected. ### Claim 34 (depends on 32) A semiconductor memory device according to claim 32, wherein said output nodes individually output different voltages in a case of a first operation which said plurality of output nodes are unconnected and output the same voltage in a case of a second operation which said plurality of output nodes are connected. ### Claim 35 (depends on 33) A semiconductor memory device according to claim 33, wherein said second operation is an operation of data erase operation. ### Claim 36 (depends on 27) A semiconductor memory device according to claim 27, wherein said change of circuit structure is an change of the number of stages. ### Claim 37 A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged on a semiconductor substrate; and a pump circuit having first and second output nodes for providing a predetermined voltage to said plurality of memory cells, wherein said pump circuit has at least first and second voltage generating circuits, each having first and second output terminals, the second output terminals of said first and second voltage generating circuits are connected respectively to said second output nodes, the first output terminal of said first voltage generating circuit is connected to said first output node, and the first output terminal of said second voltage generating circuit is connected to the input terminal of said first voltage generating circuit. ### Claim 38 (depends on 37) A semiconductor memory device according to claim 37, wherein said pump circuit has a plurality of voltage generating circuits, each having first and second output terminals, the second output terminals of said plurality of voltage generating circuits being connected respectively to said second output nodes, the first output terminals of said plurality of voltage generating circuits being connected respectively to the input terminals of the voltage generating circuits of the next stage, and the output terminals of the final stage of said plurality of voltage generating circuits being connected respectively first output nodes. ### Claim 39 (depends on 37) A semiconductor memory device according to claim 37, wherein said pump circuit further has third output node, and has a plurality of voltage generating circuits, each having first, second and third output terminals, the third output terminals of said plurality of voltage generating circuits is connected respectively to said third output nodes, the second output terminals of said plurality of voltage generating circuits is connected respectively to one of said second output nodes and the input terminals of the voltage generating circuit of the next stage, the first output terminals of said plurality of voltage generating circuits being connected respectively to the input terminals of the voltage generating circuits of the next stage, and the first output terminals of the final stage of said plurality of voltage generating circuits being connected respectively first output nodes. ### Claim 40 (depends on 37) A semiconductor memory device according to claim 37, wherein each of said plurality of voltage generating circuits has a pump circuit and a voltage limiter circuit and the operation of all the voltage limiter circuits is stopped except a single voltage limiter circuit. ### Claim 41 (depends on 40) A semiconductor memory device according to claim 40, wherein said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 42 (depends on 41) A semiconductor memory device according to claim 41, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 43 A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in matrix on a semiconductor substrate; and a pump circuit having a plurality of output nodes and outputs a predetermined voltage to said plurality of memory cells, wherein said pump circuit has a different structure when a different node among said plurality of output nodes outputs a voltage. ### Claim 44 (depends on 43) A semiconductor memory device according to claim 43, wherein each of said plurality of voltage generating circuits has a pump circuit and a voltage limiter circuit and the operation of all the voltage limiter circuits is stopped except a single voltage limiter circuit. ### Claim 45 (depends on 44) A semiconductor memory device according to claim 44, wherein said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 46 (depends on 45) A semiconductor memory device according to claim 45, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 47 A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in matrix on a semiconductor substrate; and a pump circuit having a plurality of output nodes and outputs a predetermined voltage to said plurality of memory cells, wherein said pump circuit has a different number of stages when a different node among said plurality of output nodes outputs a voltage. ### Claim 48 (depends on 47) A semiconductor memory device according to claim 47, wherein each of said plurality of voltage generating circuits has a pump circuit and a voltage limiter circuit and the operation of all the voltage limiter circuits is stopped except a single voltage limiter circuit when the nodes are connected by said switching circuit. ### Claim 49 (depends on 48) A semiconductor memory device according to claim 48, wherein said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 50 (depends on 49) A semiconductor memory device according to claim 49, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 51 (depends on 14) A semiconductor memory device according to claim 14, wherein in a case of one of connecting and unconnecting output nodes of series-connceted circuit to output nodes of said third voltage generating circuit, at least one of said first, second and third voltage generating circuit changes in structure. ### Claim 52 (depends on 51) A semiconductor memory device according to claim 51, wherein each of said plurality of voltage generating circuits has a pump circuit and a voltage limiter circuit and the operation of all the voltage limiter circuits is stopped except a single voltage limiter circuit when the nodes are connected by said exchange circuit. ### Claim 53 (depends on 52) A semiconductor memory device according to claim 52, wherein said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 54 (depends on 53) A semiconductor memory device according to claim 53, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 55 (depends on 51) A semiconductor memory device according to claim 51, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, and the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit. ### Claim 56 (depends on 51) A semiconductor memory device according to claim 51, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit, and operations of first and second voltage limiter circuits are suspended. ### Claim 57 (depends on 51) A semiconductor memory device according to claim 51, wherein said output nodes individually output different voltages in a case of a first operation which said plurality of output nodes are unconnected and output the same voltage in a case of a second operation which said plurality of output nodes are connected. ### Claim 58 (depends on 56) A semiconductor memory device according to claim 56, wherein said output nodes individually output different voltages in a case of a first operation which said plurality of output nodes are unconnected and output the same voltage in a case of a second operation which said plurality of output nodes are connected. ### Claim 59 (depends on 57) A semiconductor memory device according to claim 57, wherein said second operation is an operation of data erase operation. ### Claim 60 (depends on 51) A semiconductor memory device according to claim 51, wherein said change of circuit structure is an change of the number of stages. ### Claim 61 (depends on 51) A semiconductor memory device according to claim 51, wherein at least one of said first and second voltage generating circuit changes in structure. ### Claim 62 (depends on 61) A semiconductor memory device according to claim 61, wherein each of said plurality of voltage generating circuits has a pump circuit and a voltage limiter circuit and the operation of all the voltage limiter circuits is stopped except a single voltage limiter circuit when the nodes are connected by said exchange circuit. ### Claim 63 (depends on 62) A semiconductor memory device according to claim 62, wherein said pump circuit has a plurality of capacitors connected to the plurality of nodes connected in series and in a plurality of stages. ### Claim 64 (depends on 63) A semiconductor memory device according to claim 63, wherein said pump circuit changes the number of stages depending on the operation. ### Claim 65 (depends on 61) A semiconductor memory device according to claim 61, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, and the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit. ### Claim 66 (depends on 61) A semiconductor memory device according to claim 61, wherein said first voltage generating circuit comprises a first pump circuit and a first voltage limiter circuit, said second voltage generating circuit comprises a second pump circuit and a second voltage limiter circuit, said third voltage generating circuit comprises a third pump circuit and a third voltage limiter circuit, the operation of at least one of the first and second voltage limiter circuits is suspended when the first and second voltage generating circuits are connected in series by said exchange circuit, and operations of first and second voltage limiter circuits are suspended. ### Claim 67 (depends on 61) A semiconductor memory device according to claim 61, wherein said output nodes individually output different voltages in a case of a first operation which said plurality of output nodes are unconnected and output the same voltage in a case of a second operation which said plurality of output nodes are connected. ### Claim 68 (depends on 61) A semiconductor memory device according to claim 61, wherein said output nodes individually output different voltages in a case of a first operation which said plurality of output nodes are unconnected and output the same voltage in a case of a second operation which said plurality of output nodes are connected. ### Claim 69 (depends on 61) A semiconductor memory device according to claim 61, wherein said second operation is an operation of data erase operation. ### Claim 70 (depends on 61) A semiconductor memory device according to claim 61, wherein said change of circuit structure is an change of the number of stages.