# US 5,706,237 A · Self-restore circuit with soft error protection for dynamic logic circuits

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- Number: US 5,706,237 A
- Document ID: US5706237A
- Status: Granted
- Kind: A
- Application number: 08/729,823
- Filed: 1996-10-08
- Granted: 1998-01-06
- Earliest claimed: 1996-10-08
- Assignees: International Business Machines Corporation
- Inventors: Michael Kevin Ciraula; George McNeil Lattimore; Terry Lee Leasure; Gus Wai-Yan Yeung
- Web page: https://patentgrep.com/patent/US5706237A

## CPC

- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/4125: {Cells incorporating circuit means for protecting against loss of information}
- G11C 11/419: Read-write [R-W] circuits
- G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An improved self-restore circuit and method for restoring the output line of a dynamic logic circuit. The self-restore circuit includes two transistors connected in series between the output line and the reference voltage node. The first transistor activates after an evaluation of the output line, while the second transistor only activates subsequent to the activation of the first transistor and the completion of an evaluation cycle. The self-restore circuit reduces the power consumption and safeguards against any soft error hits, wherein the second transistor protects against any soft error hits by actively pulling up the output line to the appropriate voltage.

## Claims

### Claim 1

A self-restore circuit for restoring a dynamic logic circuit comprising:
an output line of said dynamic logic circuit, wherein said output line discharges after an evaluation cycle;
first transistor and a second transistor connected in series between said output line and a reference voltage node, wherein said first transistor is activated after an evaluation of said output line, and said second transistor is only activated subsequent to activation of said first transistor in response to an indication that the said evaluation cycle is complete; and
means for restoring said output line of said dynamic logic circuit in response to activation of said first transistor and said second transistor.

### Claim 2 (depends on 1)

A self-restore circuit according to claim 1, wherein said indication that said evaluation cycle is complete includes an output of a logic gate; said logic gate having as inputs a plurality of input evaluation lines, wherein each of said plurality of input evaluation lines determines whether said evaluation cycle is still active.

### Claim 3 (depends on 2)

A self-restore circuit according to claim 2, wherein said logic gate is an OR gate skewed to bigger P-channel.

### Claim 4 (depends on 1)

A self-restore circuit according to claim 1, and further comprising a half latch for completing said restoring of the said output line of said dynamic logic circuit; said half latch activating in response to said output line being charged.

### Claim 5 (depends on 1)

A self-restore circuit according to claim 1, and further comprising an output driver connected to said output line, wherein said output driver is skewed to bigger P-channel.

### Claim 6 (depends on 1)

A self-restore circuit according to claim 1, wherein said output line is automatically restored in response to an error causing a drop on said output line.

### Claim 7 (depends on 1)

A self-restore circuit according to claim 1, wherein said means for restoring said output line of said dynamic logic circuit in response to activation of said first transistor and said second transistor includes an electric current.

### Claim 8 (depends on 1)

A self-restore circuit according to claim 1, wherein said dynamic logic circuit is a dynamic Or-gate.

### Claim 9 (depends on 1)

A self-restore circuit according to claim 1, wherein said dynamic logic circuit is a dynamic multiplexer.

### Claim 10

A method of restoring an output line of a dynamic logic circuit; said dynamic logic circuit including a first transistor and a second transistor coupled in series between said output line and a reference voltage node, comprising the steps of:
evaluating the output line of said dynamic logic circuit;
activating said first transistor in response to the discharge of said output line; and
activating said second transistor only after activation of said first transistor, in response to an indication that the evaluation cycle is complete.

### Claim 11 (depends on 10)

The method of claim 10, including the further step of activating a half latch in response to said output line being restored; said half latch holding said output line at the voltage level of said reference node until next said evaluation cycle.

### Claim 12 (depends on 10)

The method of claim 10, including the further step of automatically restoring the output line in response to noise causing a drop on said output line.

### Claim 13

A memory device comprising:
a memory cell array having a plurality of memory cells, said memory cells being arranged at positions where a plurality of bit lines cross a plurality of word lines;
a selection signal for selecting one of said memory cells in accordance with a data writing or reading operation; and
a restore circuit for restoring said memory device, including:
an output line of said memory device, wherein said output line discharges after an evaluation cycle;
first transistor and a second transistor connected in series between said output line and a reference voltage node, wherein said first transistor is activated after an evaluation of said output line, and said second transistor is only activated subsequent to activation of said first transistor in response to an indication that the said evaluation cycle is complete; and
means for restoring said output line of said memory device in response to activation of said first transistor and said second transistor.

### Claim 14 (depends on 13)

A memory device as in claim 13 wherein said indication that said evaluation cycle is complete includes an output of a logic gate; said logic gate having as inputs a plurality of input evaluation lines, wherein each of said plurality of input evaluation lines determines whether said evaluation cycle is still active.

### Claim 15 (depends on 14)

A memory device as in claim 14 wherein said logic gate is an OR gate skewed to bigger P-channel.

### Claim 16 (depends on 13)

A memory device as in claim 13, and further comprising a half latch for completing said restoring of said output line of said memory device; said half latch activating in response to said output line being charged.

### Claim 17 (depends on 13)

A memory device as in claim 13, and further comprising an output driver connected to said output line, wherein said output driver is skewed to bigger P-channel.

### Claim 18 (depends on 13)

A memory device as in claim 13 wherein said output line is automatically restored in response to an error causing a drop on said output line.

### Claim 19 (depends on 13)

A memory device as in claim 13 wherein said means for restoring said output line of said memory device in response to activation of said first transistor and said second transistor includes an electric current.

### Claim 20 (depends on 13)

A memory device as in claim 13 wherein said memory device is a domino SRAM, including:
at least one of said plurality of local cell groups further comprising,
a plurality of core cells for storing information, and
a local bit line coupled to said plurality of core cells; and
a domino circuit coupled to said local bit line for sensing information stored in said plurality of core cells.