# US 5,706,236 A · Semiconductor memory device

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- Number: US 5,706,236 A
- Document ID: US5706236A
- Status: Granted
- Kind: A
- Application number: 08/797,044
- Filed: 1997-02-10
- Granted: 1998-01-06
- Earliest claimed: 1992-11-30
- Assignees: Fujitsu Limited
- Inventors: Yasuhiro Yamamoto
- Web page: https://patentgrep.com/patent/US5706236A

## CPC

- G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs}
- G11C 11/22: using ferroelectric elements
- G11C 11/419: Read-write [R-W] circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A sense amplifier including a presense amplifier and a main sense amplifier. The presense amplifier detects a potential difference between a pair of bit lines based on information read from memory cells and outputs a pair of current signals in accordance with the detected potential difference. The main sense amplifier amplifies the pair of current signals from the presense amplifier to output a first pair of voltage signals. The main sense amplifier provides an output current which allows the first pair of current signals to flow through the presense amplifier. The main sense amplifier includes a current supply circuit for outputting a second pair of current signals based on the amount of the first pair of current signals output from the presense amplifier, and a converting circuit for converting the second pair of current signals from the current supply circuit to voltage signals and outputting the voltage signals.

## Claims

### Claim 1

A semiconductor memory device comprising:
a plurality of memory cells for storing information;
a pair of bit lines connected to said plurality of memory cells;
a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference; and
a main sense amplifier for amplifying said first pair of current signals from said presense amplifier and generating a pair of voltage signals in proportion to a ratio of said first pair of current signals, said main sense amplifier including a current supply circuit for outputting a second pair of current signals based on the amount of said first pair of current signals of said presense amplifier, and a converting circuit, connected to said current supply circuit, for converting said second pair of current signals from said current supply circuit to said pair of voltage signals in correspondence with a ratio and regardless of amplitudes of said second pair of current signals and outputting said pair of voltage signals.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein said current supply circuit comprises:
a high-voltage power supply;
a pair of NPN transistors;
a constant-current power supply,; and
said pair of NPN transistors having respective collectors directly connected to said high-voltage power supply, respective bases supplied with a reference voltage and respective emitters connected to said constant-current power supply, for providing said output current to said presense amplifier from said emitters of said pair of NPN transistors and outputting said second pair of current signals to said converting circuit from said respective emitters of said NPN transistors.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein said converting circuit comprises:
a pair of NPN transistors;
a constant-current power supply; and
first and second resistors having a substantially same resistance as one another, and
said NPN transistors having respective emitters connected together and to said constant-current power supply, respective collectors connected to respectively via said first and second resistors to a high-voltage power supply, and respective bases supplied with said second pair of current signals output from said current supply circuit, said pair of voltage signals being respectively output from said collectors of said NPN transistors.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a bit line equalizer connected to said pair of bit lines and between said plurality of memory cells on one side and said presense and main sense amplifiers on another side, to reset potentials of said bit lines to a same potential when said bit lines are not selected.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a block of pairs of bit lines containing said pair of bit lines;
a block equalizer connected to said pair of bit lines between said plurality of memory cells on one side and the presense and main sense amplifiers on another side, to reset potentials of said pair of bit lines to a same potential when said block containing said pair of bit lines is not selected.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, further comprising column switches connected to said pair of bit lines between said memory cells on one side and the presense and main sense amplifiers on another side, said column switches being conductive when said pair of bit lines are selected.

### Claim 7

A semiconductor memory device comprising:
a plurality of memory cells for storing information;
a pair of bit lines connected to said plurality of memory cells;
a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference;
a main sense amplifier for amplifying said first pair of current signals from said presense amplifier and generating a pair of voltage signals based upon a ratio of said first pair of current signals, said main sense amplifier including a current supply circuit for outputting a second pair of current signals based on the amount of said first pair of current signals of said presense amplifier, and a converting circuit, connected to said current supply circuit, for converting said second pair of current signals from said current supply circuit to said pair of voltage signals in correspondence with a ratio of said second pair of current signals and outputting said pair of voltage signals;
a write amplifier, connected to said pair of bit lines, for amplifying and outputting write data to said pair of bit lines to be written in said plurality of memory cells; and
write drivers connected to said pair of bit lines and between said presense and main sense amplifiers on one side and the write amplifier on another side, for selectively enabling transmission of said write data from said write amplifier pair of bit lines.

### Claim 8

A semiconductor memory device comprising:
a plurality of memory cells for storing information;
a pair of bit lines connected to said plurality of memory cells;
a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference; and
a main sense amplifier for amplifying said first pair of current signals from the presense amplifier, for outputting a pair of voltage signals in proportion to a ratio of said first pair of current signals, said main sense amplifier further comprising;
a current supply circuit including
a high-voltage power supply,
a first pair of NPN transistors,
a first constant-current power supply, and
said first pair of NPN transistors having respective bases supplied with a reference voltage and respective emitters connected to said first constant-current power supply, for providing the output current to said presense amplifier from said emitters of said first pair of NPN transistors and for outputting a second pair of current signals from said respective emitters of said first pair of NPN transistors; and
a converting circuit including
a second pair of NPN transistors,
a second constant-current power supply,
first and second resistors having a same resistance as one another, and
said second pair of NPN transistors having respective emitters connected together to said second constant-current power supply, respective collectors connected respectively via said first and second resistors to a high-voltage power supply, and bases supplied with said second pair of current signals output from said current supply circuit, for converting said second pair of current signals to said pair of voltage signals respectively output from said respective collectors of said second pair of NPN transistors in correspondence with a ratio and regardless of amplitudes of said second pair of current signals.

### Claim 9 (depends on 8)

The semiconductor memory device according to claim 8, further comprising:
a bit line equalizer connected to said pair of bit lines and between said plurality of memory cells on one side and said presense and main sense amplifiers on another side, to reset potentials of said bit lines to a same potential when said bit lines are not selected.

### Claim 10 (depends on 9)

The semiconductor memory device according to claim 9, further comprising:
a block of pairs of bit lines containing said pair of bit lines;
a block equalizer connected to said pair of bit lines between said plurality of memory cells on one side and the presense and main sense amplifiers on another side, to reset potentials of said bit lines to a same potential when said block containing said pair of bit lines is not selected.

### Claim 11

A semiconductor memory device comprising:
a plurality of memory cells for storing information;
a pair of bit lines connected to said plurality of memory cells;
a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference;
a main sense amplifier for amplifying said first pair of current signals from the presense amplifier, for outputting a pair of voltage signals based upon a ratio of said first pair of current signals, said main sense amplifier further comprising;
a current supply circuit including
a high-voltage power supply,
a first pair of NPN transistors,
a first constant-current power supply, and
said first pair of NPN transistors having respective bases supplied with a reference voltage and respective emitters connected to said first constant-current power supply, for providing the output current to said presense amplifier from said emitters of said first pair of NPN transistors and for outputting a second pair of current signals from said respective emitters of said first pair of NPN transistors; and
a converting circuit including
a second pair of NPN transistors,
a second constant-current power supply,
first and second resistors having a same resistance as one another, and
said second pair of NPN transistors having respective emitters connected together to said second constant-current power supply, respective collectors connected respectively via said first and second resistors to a high-voltage power supply, and bases supplied with said second pair of current signals output from said current supply circuit, for converting said second pair of current signals to said pair of voltage signals respectively output from said respective collectors of said second pair of NPN transistors in correspondence with a ratio of said second pair of current signals;
a bit line equalizer connected to said pair of bit lines and between said plurality of memory cells on one side and said presense and main sense amplifiers on another side, to reset potentials of said bit lines to a same potential when said bit lines are not selected;
a block of pairs of bit lines containing said pair of bit lines;
a block equalizer connected to said pair of bit lines between said plurality of memory cells on one side and the presense and main sense amplifiers on another side, to reset potentials of said bit lines to a same potential when said block containing said pair of bit lines is not selected;
a write amplifier, connected to said pair of bit lines, for amplifying and outputting write data to said pair of bit lines to be written in said plurality of memory cells; and
write drivers connected to said pair of bit lines and between said presense and main sense amplifiers on one side and the write amplifier on another side, for selectively enabling transmission of said write data from said write amplifier pair of bit lines.

### Claim 12

A semiconductor memory device, comprising:
a plurality of memory cells storing information;
a pair of bit lines connected to said plurality of memory cells, said pair of bit lines forming a potential difference based upon said information;
a presense amplifier detecting the potential difference between said pair of bit lines and outputting a pair of current signals in accordance with the potential difference; and
a main sense amplifier amplifying said pair of current signals from said presense amplifier and converting said pair of current signals to output voltage signals based upon a ratio of said pair of current signals, said main sense amplifier comprising;
a current supply circuit suppressing variations in said pair of current signals and, in response to said pair of current signals, outputting a pair of output current signals, and
a converting circuit converting said pair of output current signals to said output voltage signals based upon a ratio of said output current signals.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12, further comprising:
a level shifting circuit for shifting the level of said output voltage signals to shifted voltage signals.

### Claim 14 (depends on 12)

The semiconductor device as claimed in claim 12, wherein said current supply circuit comprises:
a first constant-current power supply; and
a first pair of NPN transistors, each having a collector connected directly to a high-voltage potential, a base supplied with a reference voltage and an emitter connected to said first constant-current power supply, each of said first pair of NPN transistors receiving a respective one of said currents signals from said presense amplifier and, in response, generating a respective one of said output current signals.

### Claim 15 (depends on 14)

The semiconductor device as claimed in claim 14, wherein said converting circuit comprises:
a second constant-current power supply;
first and second resistors having the same resistance, said first and second resistors having respective first ends connected to a high-voltage potential and respective second ends; and
a second pair of NPN transistors, each having an emitter connected to one another and to the second constant-current power supply, a collector connected to a respective one of the second ends of said first and second resistors, and a base connected to a respective one of said emitters of said first pair of NPN transistors and receiving a respective one of current signals from said presense amplifier.

### Claim 16

A semiconductor memory device, comprising:
a plurality of memory cells storing information;
a pair of bit lines connecting to said plurality of memory cells, said pair of bit lines forming a potential difference based upon said information;
a presense amplifier detecting the potential difference between said pair of bit lines and generating a first pair of current signals in accordance with the potential difference; and
a main sense amplifier amplifying said first pair of current signals from said presense amplifier, and comprising;
a current supply circuit suppressing variations in said first pair of current signals and, in response to said first pair of current signals, outputting a second pair of current signals have a substantially same ratio as said first pair of current signals;
a converting circuit converting said second pair of current signals to output voltage signals based upon the ratio of said second pair of current signals; and
a level shifter shifting a level of said output voltage signals.

### Claim 17

A semiconductor memory device comprising:
a plurality of memory cells for storing information;
a pair of bit lines connected to said plurality of memory cells;
a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference; and
a main sense amplifier for amplifying said first pair of current signals from said presense amplifier and generating a pair of voltage signals based upon a ratio of said first pair of current signals, said main sense amplifier including
a current supply circuit for outputting a second pair of current signals based on the amount of said first pair of current signals of said presense amplifier, and
a differential amplifying circuit having a first pair of transistors with respective bases, said bases connected directly to said presense amplifier to respectively receive said first pair of current signals, and connected to said current supply circuit, for converting said second pair of current signals from said current supply circuit to said pair of voltage signals based upon a difference between said second pair of current signals and outputting said pair of voltage signals.

### Claim 18 (depends on 17)

The semiconductor memory device according to claim 17, wherein said converting circuit comprises:
a constant-current power supply;
first and second resistors having a substantially same resistance as one another; and
said first pair of transistors are NPN transistors having respective emitters connected together and to said constant-current power supply, respective collectors connected to respectively via said first and second resistors to a high-voltage power supply, said pair of voltage signals being respectively output from said collectors of said NPN transistors.

### Claim 19 (depends on 17)

The semiconductor memory device according to claim 17, wherein said differential amplifier further comprises a single constant current supply connected to emitters of both of said pair of transistors.

### Claim 20 (depends on 17)

The semiconductor memory device according to claim 17, further comprising a level shifter for shifting the voltages of said pair of voltage signals, wherein said level shifter includes a second pair of transistors, a first one of said second pair of transistors having a base connected to a collector of a first one of said first pair of transistors, and a second one of said second pair of transistors having a base connected to a collector of a second one of said first pair of transistors.

### Claim 21 (depends on 19)

The semiconductor memory device according to claim 19, further comprising a level shifter for shifting the voltages of said pair of voltage signals, wherein said level shifter includes a second pair of transistors, a first one of said second pair of transistors having a base connected to a collector of a first one of said first pair of transistors, and a second one of said second pair of transistors having a base connected to a collector of a second one of said first pair of transistors.

### Claim 22 (depends on 20)

The semiconductor memory device according to claim 20, further comprising a pair of constant current supplies connected to emitters of respective ones of said second pair of transistors.

### Claim 23 (depends on 21)

The semiconductor memory device according to claim 21, further comprising a pair of constant current supplies connected to emitters of respective ones of said second pair of transistors.

### Claim 24

A semiconductor memory device comprising:
a plurality of memory cells for storing information;
a pair of bit lines connected to said plurality of memory cells;
a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference; and
a main sense amplifier for amplifying said first pair of current signals from said presense amplifier and generating a pair of voltage signals based upon a ratio of said first pair of current signals, said main sense amplifier including
a first transistor having a first collector directly connected to a voltage source, a first base which receives a reference voltage, and a first emitter which receives a first one of said pair of current signals at a first node,
a second transistor having a second collector directly connected to the voltage source, a second base which receives the reference voltage, and a second emitter which receives a second one of said pair of current signals at a second node, and
a differential amplifying circuit having third and fourth transistors with respective emitters connected to each other at a third node, wherein a third base of said third transistor is connected to the second node, and a fourth base of said fourth transistor is connected to the first node.

### Claim 25 (depends on 24)

The semiconductor memory device according to claim 24, further comprising:
a first constant current supply connected to the first node;
a second constant current supply connected to the second node;
a third constant current supply connected to the third node;
a first resistance element connected between a third collector of said third transistor and the voltage source; and
a second resistance element connected between a fourth collector of said fourth transistor and the voltage source.

### Claim 26 (depends on 25)

The semiconductor memory device according to claim 25, further comprising:
a fifth transistor having a fifth collector connected to the voltage source and a fifth base connected to said third collector; and
a sixth transistor having a sixth collector connected to the voltage source and a sixth base connected to said fourth collector.

### Claim 27 (depends on 26)

The semiconductor memory device according to claim 26, further comprising:
a fourth constant current supply connected to a fifth emitter of said fifth transistor; and
a fifth constant current supply connected to a sixth emitter of said sixth transistor.