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US 5,706,233 AGranted
Semiconductor memory device allowing acceleration testing, and a semi-finished product for an integrated semiconductor device that allows acceleration testing
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
Estimating the term…
Abstract
A DRAM includes a row predecoder responsive to an multi-selection signal for activating all predecode signals independent of a row address signal, and a row decoder unit responsive to the multi-selection signal for activating all decode signals independent of the row address signal. As a result, all word drivers are activated in an acceleration test independent of the row address signal, and all the word lines are driven simultaneously.
Claims18
A semiconductor memory device including a normal mode and a test mode, said semiconductor device comprising:
- a plurality of word lines;
- a plurality of bit lines crossing said word lines;
- a plurality of memory cells provided corresponding to respective crossings of said word lines and said bit lines, each memory cell connected to a corresponding word line and bit line;
- a plurality of drive means provided corresponding to said word line, each drive means for driving a corresponding word line;
- activation means responsive to an externally applied row address signal in said normal mode for selectively activating one of said drive means, and responsive to a predetermined multi-selection signal in said test mode for activating at least two of said drive means independent of said row address signal;
- and
- control means responsive to an externally applied control signal and said multi-selection signal in said test mode for controlling said activation means to activate at least two of said drive means independent of said row address signal.
4 more elements
A semiconductor memory device including a normal mode and a test mode, said semiconductor device comprising:
- a plurality of word lines;
- a plurality of bit lines crossing said word lines;
- a plurality of memory cells provided corresponding to respective crossings of said word lines and said bit lines, each memory cell connected to a corresponding word line and bit line;
- a plurality of drive means provided corresponding to said word line, each drive means for driving a corresponding word line;
- and
- activation means responsive to an externally applied row address signal in said normal mode for selectively activating one of said drive means, and responsive to a predetermined multi-selection signal in said test mode for activating at least two of said drive means independent of said row address signal,
- said activation means comprising
- a predecoder for activating any predecode signal by predecoding said row address signal in said normal mode, and for activating all said predecode signal in response to said multi-selection signal in said test mode, and
- a plurality of predecode signal lines connected to said predecoder for receiving said plurality of predecode signal, respectively,
- wherein each of said drive means comprises a word driver connected to any of said predecode signal lines for driving a corresponding word line in response to a predecode signal of a predecode signal line connected thereto.
7 more elements
A semiconductor memory device including a normal mode and a test mode, said semiconductor device comprising:
- a plurality of word lines;
- a plurality of bit lines crossing said word lines;
- a plurality of memory cells provided corresponding to respective crossings of said word lines and said bit lines, each memory cell connected to a corresponding word line and bit line;
- a plurality of drive means provided corresponding to said word line, each drive means for driving a corresponding word line;
- activation means responsive to an externally applied row address signal in said normal mode for selectively activating one of said drive means, and responsive to a predetermined multi-selection signal in said test mode for activating at least two of said drive means independent of said row address signal;
- precharge potential generation means for generating a precharge potential for said bit line;
- and
- a first potential supply means for supplying said precharge potential from said precharge potential generation means to said bit line when a first control signal is inactive, and for supplying a predetermined first test potential to said bit line in response to an externally applied second control signal when said first control signal is active.
5 more elements
A semiconductor memory device including a normal mode and a test mode, said semiconductor device comprising:
- a plurality of word lines;
- a plurality of bit lines crossing said word lines;
- a plurality of memory cells provided corresponding to respective crossings of said word lines and said bit lines, each memory cell connected to a corresponding word line and bit line;
- a plurality of drive means provided corresponding to said word line, each drive means for driving a corresponding word line;
- activation means responsive to an externally applied row address signal in said normal mode for selectively activating one of said drive means, and responsive to a predetermined multi-selection signal in said test mode for activating at least two of said drive means independent of said row address signal;
- precharge potential generation means for generating a precharge potential for said bit line;
- and
- first potential supply means for supplying said precharge potential from said precharge potential generation means to said bit line when said multi-selection signal is inactive, and for supplying a predetermined first test potential to said bit line in response to an externally applied control signal when said multi-selection signal is active.
5 more elements
A semiconductor memory device including a normal mode and a test mode, said semiconductor device comprising:
- a plurality of word lines;
- a plurality of bit lines crossing said word lines;
- a plurality of memory cells provided corresponding to respective crossings of said word lines and said bit lines, each memory cell connected to a corresponding word line and bit line;
- a plurality of drive means provided corresponding to said word line, each drive means for driving a corresponding word line;
- activation means responsive to an externally applied row address signal in said normal mode for selectively activating one of said drive means, and responsive to a predetermined multi-selection signal in said test mode for activating at least two of said drive means independent of said row address signal;
- cell plate potential generation means for generating a cell plate potential for a cell plate of said memory cell;
- and
- second potential supply means for supplying said cell plate potential from said cell plate potential generation means to a cell plate of said memory cell when said multi-selection signal is inactive, and for supplying a predetermined second test potential to a cell plate of said memory cell in response to an externally applied control signal when said multi-selection signal is active.
5 more elements
A semiconductor memory device including a normal mode and a test mode, said semiconductor device comprising:
- a plurality of word lines;
- a plurality of bit lines crossing said word lines;
- a plurality of memory cells provided corresponding to respective crossings of said word lines and said bit lines, each memory cell connected to a corresponding word line and bit line;
- a plurality of drive means provided corresponding to said word line, each drive means for driving a corresponding word line;
- activation means responsive to an externally applied row address signal in said normal mode for selectively activating one of said drive means, and responsive to a predetermined multi-selection signal in said test mode for activating at least two of said drive means independent of said row address signal;
- and
- multi-selection signal generation means responsive to a predetermined timing of externally applied plurality of control signals for generating said multi-selection signal.
4 more elements
A semiconductor memory device including a normal mode and a test mode, said semiconductor device comprising:
- a plurality of word lines;
- a plurality of bit lines crossing said word lines;
- a plurality of memory cells provided corresponding to respective crossings of said word lines and said bit lines, each memory cell connected to a corresponding word line and bit line;
- a plurality of drive means provided corresponding to said word line, each drive means for driving a corresponding word line;
- activation means responsive to an externally applied row address signal in said normal mode for selectively activating one of said drive means, and responsive to a predetermined multi-selection signal in said test mode for activating at least two of said drive means independent of said row address signal;
- and
- a multi-selection pad externally receiving said multi-selection signal.
4 more elements
A semiconductor memory device including a normal mode and a test mode, said semiconductor device comprising:
- a plurality of word lines;
- a plurality of bit lines crossing said word lines;
- a plurality of memory cells provided corresponding to respective crossings of said word lines and said bit lines, each memory cell connected to a corresponding word line and bit line;
- a plurality of drive means provided corresponding to said word line, each drive means for driving a corresponding word line;
- activation means responsive to an externally applied row address signal in said normal mode for selectively activating one of said drive means, and responsive to a predetermined multi-selection signal in said test mode for activating at least two of said drive means independent of said row address signal;
- boosted potential generation means for generating an internal boosted potential higher than a power supply potential;
- and
- word line drive potential supply means responsive to said multi-selection signal for selectively supplying said internal boosted potential from said boosted potential generation means and a predetermined test potential to said drive means,
- wherein each of said drive means provides the supplied potential to said corresponding word line to drive said corresponding word line.
6 more elements
A semiconductor memory device including a normal mode and a test mode, said semiconductor memory device comprising:
- a plurality of word line groups, each including a plurality of word lines,
- a plurality of bit lines crossing said word lines,
- a plurality of memory cells provided corresponding to respective crossings of said word lines and said bit lines, each memory cell connected to a corresponding word line and bit line,
- a plurality of drive means provided corresponding to said word lines, each drive means for driving a corresponding word line,
- activation means responsive to an externally applied row address signal for selectively activating one of said drive means in said normal mode, and
- means for providing a plurality of multi-selection signals in a test mode, each of the plurality of multi-selection signals being provided to a corresponding word line group, said activation means being response to the plurality of multi-selection signals in said test mode for activating all the drive means corresponding to one of said word line groups while maintaining inactive all the drive means corresponding to the other of the word line groups.
3 more elements
A semiconductor memory device including a normal mode and a test mode, said semiconductor memory device comprising:
- a semiconductor substrate,
- a plurality of word lines formed on said semiconductor substrate,
- a plurality of bit lines crossing said word lines, formed on said semiconductor substrate,
- a plurality of memory cells provided corresponding to respective crossings of said word lines and said bit lines, each memory cell comprising a cell capacitor including a cell plate and a storage node formed on said semiconductor substrate for storing data, and an access transistor including a gate electrode formed on said semiconductor substrate and connected to a corresponding word line, one source/drain region formed in said semiconductor substrate and connected to a corresponding bit line, and another source/drain region formed in said semiconductor substrate and connected to the storage node of said cell capacitor,
- a plurality of drive means provided corresponding to said word lines, each drive means for driving a corresponding word line,
- activation means responsive to an externally applied row address signal in said normal mode for selectively activating one of said drive means, and responsive to a predetermined multi-selection signal in said test mode for activating at least two of said drive means independent of said row address signal,
- substrate potential supply means responsive to said multi-selection signal for selectively supplying a predetermined substrate potential and a predetermined first test potential to said semiconductor substrate,
- cell place potential generation means for generating a cell plate potential for said cell plate, and
- cell plate potential supply means responsive to said multi-selection signal for selectively supplying said cell plate potential from said cell plate potential generation means and a predetermined second test potential to said cell plate.
6 more elements
Dependencies are inferred from the claim text.