# US 5,706,232 A · Semiconductor memory with multiple clocking for test mode entry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,706,232 A - Document ID: US5706232A - Status: Granted - Kind: A - Application number: 08/424,722 - Filed: 1995-04-18 - Granted: 1998-01-06 - Earliest claimed: 1990-08-17 - Assignees: SGS-Thomson Microelectronics S.A. - Inventors: David Charles McClure; Thomas Allyn Coker - Web page: https://patentgrep.com/patent/US5706232A ## CPC - G11C 29/46: Test trigger logic - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function. ## Claims ### Claim 1 A static random access memory having a normal operating mode, and having a special operating mode enabled by an enable signal, comprising: a plurality of memory cells, arranged in rows and columns; circuitry for accessing at least one of said memory cells in the normal operating mode, responsive to receiving a memory address; output circuitry, for presenting the contents of the accessed memory cell in the normal operating mode; a first terminal for receiving pulses of a mode initiate signal indicating entry into the special operating mode; and an enable circuit, having an input coupled to said first terminal, and having an output for presenting said enable signal responsive to receipt, at said first terminal, of a plurality of pulses of said mode initiate signal, circuit also responsive to the first state of said signal at the wherein said enable circuit comprises sequential logic for storing a state indicating the receipt of a single pulse of said mode initiate signal and for not presenting said enable signal responsive to receipt, at said first terminal, of a single pulse of said mode initiate signal, said enable circuit comprising: a plurality of latch circuits, each clocked responsive to receipt of a pulse of said mode initiate signal, wherein the output of a last one of said latch circuits presents said enable signal, and wherein said plurality of latch circuits are connected in series in such a manner that the last one of said latch circuits presents said enable signal responsive to receipt of a plurality of pulses of said mode initiate signal, wherein each of said plurality of latch circuits have a preferred state on power-up of the circuit in such a manner as to indicate that no pulses of said mode initiate signal have been received. ### Claim 2 (depends on 1) The memory of claim 1, wherein said accessing circuitry and output circuitry are responsive to signals having an amplitude in a range between first and second limits when the circuit is in the normal operating mode; and wherein said mode initiate signal received at said first terminal comprises a pulse having an amplitude outside of said range. ### Claim 3 (depends on 1) The memory cell of claim 1, further comprising: a second terminal, for receiving a mode select signal; and an evaluation circuit, for coupling said first and second terminals to said enable circuit by having inputs coupled to said first and second terminals and having an output coupled to said input of said enable circuit, and for presenting a match signal to said enable circuit responsive to the receipt of a pulse of said mode initiate signal in conjunction with said mode select signal. ### Claim 4 (depends on 3) The memory cell of claim 3, wherein said second terminal receives first and second mode select signals, for selecting first and second special operating modes; and wherein said evaluation circuit presents, at its output, first and second match signals responsive to the receipt of a pulse of said mode initiate signal in conjunction with said first and second mode select signals, respectively. ### Claim 5 (depends on 4) The memory of claim 4, wherein said enable circuit comprises: a first enable circuit, having an input coupled to the output of said evaluation circuit, and having an output for presenting a first enable signal ;responsive to receipt of a plurality of said first match signals, wherein said first enable circuit comprises sequential logic for storing a state indicating the receipt of a single first match signal and for not presenting said first enable signal responsive to receipt of a single first match signal; and a second enable circuit, having an input coupled to the output of said evaluation circuit, and having an output for presenting a second enable signal responsive to receipt of a plurality of said second match signals, wherein said second enable circuit comprises sequential logic for storing a state indicating the receipt of a single second match signal and for not presenting said second enable signal responsive to receipt of a single second match signal. ### Claim 6 (depends on 5) The memory of claim 5, wherein said first enable circuit comprises: a plurality of latch circuits clocked responsive to receipt of said first match signals, wherein the output of a last one of said latch circuits presents said first enable signal, and wherein said plurality of latch circuits, are connected in series in such a manner that the last one of said latch circuits presents said first enable signal responsive to receipt of a plurality of said first match signals; and wherein said second enable circuit comprises: a plurality of latch circuits clocked responsive to receipt of said second match signals, wherein the output of a last one of said latch circuits presents said second enable signal, and wherein said plurality of latch circuits are connected in series in such a manner that the last one of said latch circuits presents said second enable signal responsive to receipt of a plurality of said second match signals. ### Claim 7 (depends on 6) The memory of claim 6, wherein said accessing circuitry and output circuitry are responsive to signals having an amplitude in a range between first and second limits when the circuit is in the normal operating mode; and wherein said mode initiate signal received at said first terminal comprises a pulse having an amplitude outside of said range. ### Claim 8 (depends on 7) The memory of claim 7, further comprising: an overvoltage detection circuit, coupled between said first terminal and said evaluation circuit, for detecting receipt of said mode initiate signal at said first terminal. ### Claim 9 A static random access memory having a normal operating mode, and having a special operating mode enabled by an enable signal, comprising: a plurality of memory cells, arranged in rows and columns; circuitry for accessing at least one of said memory cells in the normal operating mode, responsive to receiving a memory address; output circuitry, for presenting the contents of the accessed memory cell in the normal operating mode; a first terminal for receiving pulses of a mode initiate signal indicating entry into a special operating mode; and an enable circuit, having an input coupled to said first terminal, and having an output for presenting said enable signal responsive to receipt, at said first terminal, of a plurality of pulses of said mode initiate signal, wherein said enable circuit comprises sequential logic for storing a state indicating the receipt of a single pulse of said mode initiate signal and for not presenting said enable signal responsive to receipt, at said first terminal, of a single pulse of said mode initiate signal; wherein said accessing circuitry and output circuitry are responsive to signals having an amplitude in a range between first and second limits when the circuit is in the normal operating mode; and wherein said mode initiate signal received at said first terminal comprises a pulse having an amplitude outside of said range. ### Claim 10 (depends on 9) The memory of claim 9, further comprising: an overvoltage detection circuit, coupled between said first terminal and said enable circuit, for detecting receipt of said mode initiate signal at said first terminal. ### Claim 11 (depends on 9) The memory cell of claim 9, further comprising: a second terminal, for receiving a mode select signal; and an evaluation circuit, for coupling said first and second terminals to said enable circuit by having inputs coupled to said first and second terminals and having an output coupled to said input of said enable circuit, and for presenting a match signal to said enable circuit responsive to the receipt of a pulse of said mode initiate signal in conjunction with said mode select signal. ### Claim 12 (depends on 11) The memory cell of claim 11, wherein said second terminal receives first and second mode select signals, for selecting first and second special operating modes; and wherein said evaluation circuit presents, at its output, first and second match signals responsive to the receipt of a pulse of said mode initiate signal in conjunction with said first and second mode select signals, respectively. ### Claim 13 (depends on 12) The memory of claim 12, wherein said enable circuit comprises: a first enable circuit, having an input coupled to the output of said evaluation circuit, and having an output for presenting a first enable signal responsive to receipt of a plurality of said first match signals, wherein said first enable circuit comprises sequential logic for storing a state indicating the receipt of a single first match signal and for not presenting said first enable signal responsive to receipt of a single first match signal; and a second enable circuit, having an input coupled to the output of said evaluation circuit, and having an output for presenting a second enable signal responsive to receipt of a plurality of said second match signals, wherein said second enable circuit comprises sequential logic for storing a state indicating the receipt of a single second match signal and for not presenting said second enable signal responsive to receipt of a single second match signal. ### Claim 14 (depends on 13) The memory of claim 13, wherein said first enable circuit comprises: a plurality of latch circuits clocked responsive to receipt of said first match signals, wherein the output of a last one of said latch circuits presents said first enable signal, and wherein said plurality of latch circuits are connected in series in such a manner that the last one of said latch circuits presents said first enable signal responsive to receipt of a plurality of said first match signals; and wherein said second enable circuit comprises: a plurality of latch circuits clocked responsive to receipt of said second match signals, wherein the output of a last one of said latch circuits presents said second enable signal, and wherein said plurality of latch circuits are connected in series in such a manner that the last one of said latch circuits presents said second enable signal responsive to receipt of a plurality of said second match signals. ### Claim 15 A method for enabling a special operating mode of a static random access memory, comprising: receiving a plurality of mode initiate pulses at a first terminal of said circuit; and generating a special mode enable signal responsive to receipt of said plurality of mode initiate pulses, wherein said special mode enable signal is not generated responsive to receipt of a single one of said plurality of mode initiate pulses; wherein, in a normal operating mode, said memory presents the contents of at least one selected memory cell at an output terminal responsive to signals received at said first terminal having an amplitude in a range between first and second limits; and wherein each of said plurality of mode initiate pulses comprises a signal having an amplitude outside of said range. ### Claim 16 (depends on 15) The method of claim 15, wherein the step of generating the special mode enable signal comprises: clocking a series of latches responsive to receipt of each of said mode initiate pulses. ### Claim 17 (depends on 16) The method of claim 16, wherein the step of generating the special mode enable signal further comprises: presenting a data state to the first one of said series of latches so that said data state is clocked into said first one of said series of latches responsive to receipt of a first one of said plurality of mode initiate pulses; and wherein said series of latches are connected in series in such a manner that the last one of said series of latches presents the special mode enable signal at its output after said clocking step has been performed for said plurality of mode initiate pulses.