# US 5,706,182 A · Converter topologies with multiple windings

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- Number: US 5,706,182 A
- Document ID: US5706182A
- Status: Granted
- Kind: A
- Application number: 08/775,502
- Filed: 1996-12-31
- Granted: 1998-01-06
- Earliest claimed: 1996-12-31
- Assignees: Compaq Computer Corporation
- Inventors: Richard A. Faulk
- Web page: https://patentgrep.com/patent/US5706182A

## CPC

- H02M 3/005: {using Cuk converters}
- H02M 3/28: using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M 3/33569: {having several active switching elements (H02M3/3353 takes precedence)}
- H02M 3/1557: {Single ended primary inductor converters [SEPIC]}
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

Converter topologies in which two separate switching transistors and two capacitors are used on the input side. Preferably the two transistors are switched alternately, to alternately pull down different nodes in an inductor-capacitor chain. Two capacitors are interposed in series between an input inductor on the input and a transformer primary winding. Preferably the two transistors are connected with their parasitic diodes in opposite senses, so that one can source current from a first node to ground when off, and the other can sink current from a second node to ground when off.

## Claims

### Claim 1

A power converter circuit comprising:
an input winding operatively connected at a first end thereof to an input power terminal;
an output winding inductively coupled to said input winding, and operatively connected to provide current at an output terminal;
an intermediate capacitor and a primary winding, both connected in series with said input winding;
switch connected to selectably vary the voltage of a node between said input and primary windings; and
secondary winding connected in parallel with said output winding, and inductively coupled to said primary winding but not to said input winding.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein all said windings are wound on a low-profile integrated magnetic structure which includes multiple separate flux paths, and some of said windings are decoupled from others of said windings.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein all said windings are wound on a common magnetic structure.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein said power output terminals are configured to provide power to a computer system.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein said power output terminals are configured to provide power to an electrical storage and recharging system.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein said switch is a VDMOS power transistor.

### Claim 7

A power converter circuit, comprising:
an input winding operatively connected at a first end thereof to an input power terminal;
a first intermediate capacitor, a second intermediate capacitor, and a primary winding, all jointly connected in series with said input winding;
first and second switches connected to selectably vary the voltage of first and second nodes of one of said intermediate capacitors; and
a secondary winding inductively coupled to said primary winding and to said input winding, and operatively connected to provide current at an output terminal.

### Claim 8 (depends on 7)

The circuit of claim 7, wherein all said windings are wound on a low-profile integrated magnetic structure which includes multiple separate flux paths, and some of said windings are decoupled from others of said windings.

### Claim 9 (depends on 7)

The circuit of claim 7, wherein said power output terminals are connected to provide power to a portable computer system.

### Claim 10 (depends on 7)

The circuit of claim 7, wherein said power output terminals are operatively connected to charge a battery.

### Claim 11 (depends on 7)

The circuit of claim 7, wherein at least one said capacitor is electrolytic.

### Claim 12 (depends on 7)

The circuit of claim 7, wherein all said windings are wound on a common magnetic structure.

### Claim 13 (depends on 7)

The circuit of claim 7, wherein each said switch is a VDMOS power transistor.

### Claim 14

A circuit, comprising:
an input winding operatively connected at a first end thereof to an input power terminal;
an output winding inductively coupled to said input winding, and operatively connected to provide current at an output terminal;
a first intermediate capacitor, a second intermediate capacitor, and a primary winding, all jointly connected in series with said input winding;
first and second switches connected to selectably vary the voltage of first and second nodes of one of said intermediate capacitors; and
a secondary winding connected in parallel with said output winding, and inductively coupled to said primary winding but not to said input winding.

### Claim 15 (depends on 14)

The circuit of claim 14, wherein all said windings are wound on a low-profile integrated magnetic structure which includes multiple separate flux paths, and some of said windings are decoupled from others of said windings.

### Claim 16 (depends on 14)

The circuit of claim 14, wherein said power output terminals are connected to provide power to a portable computer system.

### Claim 17 (depends on 14)

The circuit of claim 14, wherein said power output terminals are operatively connected to charge a battery.

### Claim 18 (depends on 14)

The circuit of claim 14, wherein all said windings are wound on a common magnetic structure.

### Claim 19 (depends on 14)

The circuit of claim 14, wherein at least one said capacitor is electrolytic.

### Claim 20 (depends on 14)

The circuit of claim 14, wherein said switch is a VDMOS power transistor.