# US 5,706,156 A · Semiconductor device having an ESD protective circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,706,156 A - Document ID: US5706156A - Status: Granted - Kind: A - Application number: 08/591,025 - Filed: 1996-01-25 - Granted: 1998-01-06 - Earliest claimed: 1995-01-25 - Assignees: NEC Corporation - Inventors: Kaoru Narita - Web page: https://patentgrep.com/patent/US5706156A ## CPC - H10D 89/811: {using FETs as protective elements} - H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs} - H10D 89/611: {using diodes as protective elements} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device has a protective circuitry including a common discharge line, a first protective device connected between one of input/output terminals and the discharge line, and a second protective device connected between one of Vcc and ground terminals and the discharge line. The second protective device has an on-resistance as much as 1/2 of the on-resistance of the first protective device. Each of the power terminals and ground terminals generally has a large capacitance to accumulate a large amount of electric charge during a CDM test after charging of the semiconductor device as a whole. The low on-resistance prevents the inner circuit and input/output buffers of the semiconductor device from being applied with a higher potential during subsequent grounding of the semiconductor device in the CDM test. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; an inner circuit formed on said substrate; an external terminal group disposed for said inner circuit and including a plurality of first terminals and a plurality of second terminals; and a protective circuitry including: a common discharge line; a first protective device connected between each of said first terminals and said common discharge line; and a second protective device connected between each of said second terminals and said common discharge line, each of said first terminals having a first parasitic capacitance, each of said second terminals having a second parasitic capacitance larger than said first parasitic capacitance, said first protective device having a first on-resistance, said second protective device having a second on-resistance smaller than said first on-resistance. ### Claim 2 (depends on 1) A semiconductor device as defined in claim 1 wherein said first terminals include a plurality of input/output terminals and said second terminals include at least one of power terminals and ground terminals. ### Claim 3 (depends on 1) A semiconductor device as defined in claim 1 wherein said second protective device includes a plurality of protective elements each having a current path substantially equal to a current path of said first protective device in width. ### Claim 4 (depends on 1) A semiconductor device according to claim 1, wherein said second protective device has an on-resistance no more than 1/2 as much as the on-resistance of said first protective device. ### Claim 5 (depends on 1) A semiconductor device as defined in claim 1 wherein each of said first and second protective devices includes a clamp element. ### Claim 6 (depends on 5) A semiconductor device as defined in claim 5 wherein said clamp element comprises a bipolar transistor. ### Claim 7 (depends on 5) A semiconductor device as defined in claim 5 wherein said clamp element comprises a thyristor. ### Claim 8 (depends on 5) A semiconductor device as defined in claim 5 wherein said clamp element comprises a NMOS FET. ### Claim 9 (depends on 5) A semiconductor device as defined in claim 5 wherein each of said first and second protective devices further includes a diode connected in parallel to said clamp element. ### Claim 10 A protective circuitry for a semiconductor device including a substrate, an inner circuit formed on said substrate, an external terminal group disposed for said inner circuit and including a plurality of first terminals and a plurality of second terminals, said protective circuitry comprising: a common discharge line; a first protective device connected between each of said first terminals and said common discharge line; and a second protective device connected between each of said second terminals and said common discharge line, each of said first terminals having a first parasitic capacitance, each of said second terminals having a second parasitic capacitance larger than said first parasitic capacitance, said first protective device having a first on-resistance, said second protective device having a second on-resistance smaller than said first on-resistance. ### Claim 11 (depends on 10) A protective circuitry according to claim 10, wherein said first terminals include a plurality of input/output terminals and said second terminals include at least one of power terminals and ground terminals. ### Claim 12 (depends on 10) A protective circuitry according to claim 10, wherein said second protective device includes a plurality of protective elements each having a current path substantially equal to a current path of said first protective device in width. ### Claim 13 (depends on 10) A protective circuitry according to claim 10, wherein said second protective device has an on-resistance no more than 1/2 as much as the on-resistance of said first protective device. ### Claim 14 (depends on 10) A protective circuitry according to claim 10, wherein each of said first and second protective devices includes a clamp element. ### Claim 15 (depends on 14) A protective circuitry according to claim 14, wherein said clamp element comprises a bipolar transistor. ### Claim 16 (depends on 14) A protective circuitry according to claim 14, wherein said clamp element comprises a thyristor. ### Claim 17 (depends on 14) A protective circuitry according to claim 14, wherein said clamp element comprises a NMOS FET. ### Claim 18 (depends on 14) A protective circuitry according to claim 14, wherein each of said first and second protective devices further includes a diode connected in parallel to said clamp element.