# US 5,706,034 A · Graphic processing apparatus and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,706,034 A - Document ID: US5706034A - Status: Granted - Kind: A - Application number: 08/358,988 - Filed: 1994-12-19 - Granted: 1998-01-06 - Earliest claimed: 1990-07-27 - Assignees: Hitachi, Ltd. - Inventors: Koyo Katsura; Yasushi Fukunaga; Ryo Fujita; Kazuyoshi Koga; Takehiko Nishida - Web page: https://patentgrep.com/patent/US5706034A ## CPC - G06F 3/14: Digital output to display device {; Cooperation and interconnection of the display device with other functional units} - G09G 5/39: Control of the bit-mapped memory - G09G 5/001: {Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor} - G09G 5/363: {Graphics controllers} - G09G 5/393: Arrangements for updating the contents of the bit-mapped memory - G09G 2360/127: Updating a frame memory using a transfer of data from a source area to a destination area - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size. ## Claims ### Claim 1 A graphic processing apparatus comprising: a processor for executing an operation process; a display for displaying pixel data; a memory for storing, in an integrated manner, at least a program necessary for operation of said processor and a plurality of said pixel data produced by said processor; a display controller having a first display buffer and a second display buffer, each for buffering at least a raster portion of said pixel data stored in said memory, said display controller alternately using during subsequent display cycles, one of said first display buffer and said second display buffer as a write buffer for writing a next pixel data thereto from said memory, while using an opposite one of said first display buffer and said second display buffer as a read buffer for reading a current pixel data therefrom to said display; a comparator for comparing a time required to read a remaining said next pixel data from said memory into said write buffer with a remaining operation time required to display a remaining content of said read buffer; and a priority control means for controlling memory access priority based on a comparison made in said comparator, said priority control means generating a priority control signal indicating a first memory access priority value for high priority accessing of said display controller to said memory when a time required to read said next pixel data remaining in said memory means approaches said remaining operation time required to display said remaining content in said read buffer, and otherwise generating another priority control signal indicating a second memory access priority value for normal priority accessing of said display controller to said common memory. ### Claim 2 (depends on 1) A graphic processing apparatus as claimed in claim 1, wherein said memory integrally comprises both a main memory storage area for storing said program and a display storage area for storing said pixel data. ### Claim 3 (depends on 1) A graphic processing apparatus according to claim 1, further comprising a memory bus connected to said memory wherein said processor and said display controller access through said memory bus to said memory. ### Claim 4 A graphic processing apparatus comprising: a processor for executing an operation process; a display for displaying pixel data; a memory for storing, in an integrated manner, at least a program for executing an operation process by said processor and a plurality of said pixel data, said memory including a pair of display buffers each for holding at least a raster portion of said pixel data, a memory data supplier for supplying said current pixel data alternately stored in one of said first and second display buffer of said memory to said display; and a compare means for comparing a time required to write a remaining said next pixel data in one of said first and second display buffer with a remaining operation time to output a remaining said current pixel data from an opposite one of said first and second display buffer to said display means for providing control of priority accessing to said memory for said pixel data, so as to prioritize an access of said pixel data from said memory over a program access of said program from said memory when a time required to write a remaining said next pixel data approaches said remaining operation time required to output said current pixel data. ### Claim 5 (depends on 4) A graphic processing apparatus according to claim 4, wherein said pixel data stored in said memory is equal to or larger than at least a display capacity of said display means. ### Claim 6 (depends on 5) A graphic processing apparatus according to claim 5, wherein said memory data supplier includes buffer means for temporarily storing a series of data accessed in successive column manner by said processor. ### Claim 7 (depends on 6) A graphic processing apparatus according to claim 6, wherein a number of times of successive column accesses is varied. ### Claim 8 (depends on 4) A graphic processing apparatus according to claim 4, wherein said memory data supplier includes buffer means for temporarily storing a series of data accessed in successive column manner for supplying to said display. ### Claim 9 (depends on 5) A graphic processing apparatus according to claim 5, wherein said memory data supplier includes buffer means for temporarily storing a series of data accessed in successive column manner for supplying to said display. ### Claim 10 (depends on 8) A graphic processing apparatus according to claim 8, wherein said buffer means includes a plurality of buffers for temporarily storing a series of data accessed in successive column manner for application to said display, said plurality of buffers being connected in parallel. ### Claim 11 (depends on 9) A graphic processing apparatus according to claim 9, wherein said buffer means includes a plurality of buffers for temporarily storing a series of data accessed in successive column manner for application to said display, said plurality of buffers being connected in parallel. ### Claim 12 (depends on 4) A graphic processing apparatus as claimed in claim 4, wherein said memory integrally comprises both a main memory storage area for storing said program and a display storage area for storing said pixel data. ### Claim 13 A graphic processing apparatus comprising: a rendering processor for controlling generation of graphic data; a dynamic memory for storing, in an integrated manner, both program data and pixel data generated by said rendering processor; a display unit including a pair of display buffers for displaying content thereof to output pixel data for at least a raster stored in said dynamic memory to a display, wherein, for subsequent display cycles, one of a first display buffer and a second display buffer of said pair of display buffers is used as a write buffer for writing a next pixel data thereto, while an opposite one of said first display buffer and said second display buffer is used as a read buffer for reading a current pixel data therefrom to said display; and, a control means connected with said display unit for comparing a time required to write a next pixel data remaining in said dynamic memory to said write buffer with a remaining operation time required to display a current pixel data remaining in said read buffer; whereby a row address is designated to said dynamic memory and data in different column addresses within said designated row address are successively accessed, and a number of times of successive column accesses is varied in accordance with a result of a comparison made in said control means to assure an integrity of a display of said pixel data on said display by prioritizing accessing of said pixel data from said dynamic memory over said program data when a time required to write a remaining said next pixel data approaches said remaining operation time to display said current pixel data. ### Claim 14 (depends on 13) A graphic processing apparatus as claimed in claim 13, wherein said dynamic memory integrally comprises both a main memory storage area for storing at least one program for controlling an operation of said graphic processing apparatus and a display storage area for storing said pixel data. ### Claim 15 A graphic processing method in which pixel data to be displayed in a display unit is prepared by operation processing and stored in a memory and stored pixel data is supplied to said display unit wherein for subsequent display cycles, one of a first display buffer and a second display buffer of a pair of display buffers is used as a write buffer for writing a next pixel data thereto while an opposite one of said first display buffer and said second display buffer is used as a read buffer for reading a current pixel data therefrom to said display, and access to said memory for said operation processing and access to said memory for display are executed in accordance with a predetermined priority order among said operation processing on a data and said display data out of said memory for pixel, wherein when a time required to write a remaining said next pixel data to said write buffer approaches a remaining operation time to output said current pixel data from said read buffer to said display unit, a priority of access to said memory for display is increased over access to said memory for said operation processing in order to assure an integrity of a display of said pixel data on said display. ### Claim 16 (depends on 15) A graphic processing method according to claim 15, wherein at least an access time to said memory for said operation processing and an access time to said memory for said display are variable. ### Claim 17 (depends on 15) A graphic processing method as claimed in claim 15, comprising the further step of storing said pixel data in a display storage area of said memory, and having said memory store at least one program in a main memory storage area, wherein said display storage area and said main memory storage area are provided integrally in said memory.