# US 5,705,946 A · Low power low voltage level shifter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,705,946 A - Document ID: US5705946A - Status: Granted - Kind: A - Application number: 08/473,321 - Filed: 1995-06-07 - Granted: 1998-01-06 - Earliest claimed: 1995-06-07 - Assignees: SGS-Thomson Microelectronics S.A. - Inventors: Rong Yin - Web page: https://patentgrep.com/patent/US5705946A ## CPC - H03K 19/01707: {in asynchronous circuits} - H03K 19/0013: {in field effect transistor circuits} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A low power, low voltage level shifter is provided. The voltage level shifter includes a first switching circuit, and a second switching circuit. The first switching circuit has a first input terminal for receiving a first oscillating signal, and based on the first oscillating signal, switches the output of the first switching circuit between a first voltage level and a second voltage level. The second switching circuit has a second input terminal connected to the output terminal of the first switching circuit. The second switching circuit also has a third input terminal for receiving a second oscillating signal which is out of phase with the first oscillating signal. Based on the input signals received, the second switching circuit generates an output signal that switches between a third voltage level and a fourth voltage level at a selected rate and frequency. ## Claims ### Claim 1 A voltage level shifter comprising: a first switching circuit having a first input terminal for receiving a first oscillating signal and a first output terminal, the first switching circuit switching the first oscillating signal between a first voltage level and a second voltage level at the first output terminal; and a second switching circuit having a second input terminal connected to the first output terminal, a second output terminal, and a third input terminal for receiving a second oscillating signal, the second oscillating signal being out of phase with the first oscillating signal, the second switching circuit switching the second oscillating signal between a third voltage level and a fourth voltage level at the second output terminal based on the second oscillating signal and the switched first oscillating signal, the switched first oscillating signal controlling the switching time of the second oscillating signal switching between the third voltage level and the fourth voltage level. ### Claim 2 (depends on 1) The shifter according to claim 1 wherein the first switching circuit includes a first switch and a second switch connected in series with each other, each having a control terminal coupled to the first oscillating signal. ### Claim 3 (depends on 2) The shifter according to claim 2 wherein the first switching circuit includes: first AC coupling means coupled between the first input terminal and the first switch; second AC coupling means coupled between the first input terminal and the second switch; a first DC bias circuit coupled to the first switch; and a second DC bias circuit coupled to the second switch. ### Claim 4 (depends on 3) The shifter according to claim 3 wherein the first and second DC bias circuits are coupled to the control terminals of the first and second switches, respectively. ### Claim 5 (depends on 1) The shifter according to claim 1 wherein the second switching circuit includes: a first transistor; and a second transistor connected in series with the first transistor, the node between the two transistors defining the second output terminal, wherein the control terminals of the first and second transistors are connected to the first output terminal. ### Claim 6 (depends on 5) The shifter according to claim 5 wherein the second switching circuit further includes: a third transistor connected in series with the first transistor; and a fourth transistor connected in series with the second transistor, wherein the control terminals of the third and fourth transistors are coupled to the third input terminal. ### Claim 7 A voltage level shifter comprising: an inverter having a first output terminal and a first input terminal for receiving a first oscillating signal; and a switching circuit having a second output terminal, a second input terminal connected to the first output terminal, and a third input terminal for receiving a second oscillating signal, the second oscillating signal being out of phase with the first oscillating signal, the switching circuit for shifting the second oscillating signal between a first voltage level and a second voltage level at the second output terminal based on the second oscillating signal and the voltage level at the second input terminal, the voltage level at the second input terminal controlling the switching time of the second oscillating signal shifting between the first voltage level and the second voltage level. ### Claim 8 (depends on 7) The shifter according to claim 7 wherein the switching circuit includes: a first transistor; and a second transistor connected in series with the first transistor and defining the second output terminal therebetween, wherein the gate terminals of the first and second transistors are connected to the first output terminal. ### Claim 9 (depends on 8) The shifter according to claim 8 wherein the switching circuit further includes: a pull-up transistor connected in series with the first transistor for shifting the voltage level at the second output terminal to the first voltage level; and a pull-down transistor connected in series with the second transistor for shifting the voltage level at the second output terminal to the second voltage level, wherein the gate terminals of the pull-up and pull-down transistors are coupled to the third input terminal. ### Claim 10 A method of generating a clock signal alternating between first and second logic states, the method comprising: receiving a first oscillating signal; receiving a second oscillating signal out of phase with the first oscillating signal; switching the first oscillating signal between a first voltage level and a second voltage level; receiving the switched first oscillating signal; controlling the switching time of the alternating first and second logic states with the switched first oscillating signal; and generating the alternating first and second logic states based on the switched first oscillating signal, and the received second oscillating signal. ### Claim 11 (depends on 10) The method according to claim 10 wherein the first and second oscillating signals are substantially 180 degrees out of phase. ### Claim 12 (depends on 10) The method according to claim 10, prior to the step of generating the alternating first and second logic states, further comprising the step of shifting the second oscillating signal by a predetermined DC voltage level. ### Claim 13 A voltage level shifter comprising: a first switching circuit having a first input terminal for receiving a first oscillating signal and a first output terminal, the first switching circuit including a first switch and a second switch connected in series with each other, each having a control terminal coupled to the first oscillating signal, the first switching circuit for switching the first oscillating signal between a first voltage level and a second voltage level at the first output terminal; and a second switching circuit having a second input terminal connected to the first output terminal, a second output terminal, and a third input terminal for receiving a second oscillating signal, the second oscillating signal being out of phase with the first oscillating signal, the second switching circuit for switching the second oscillating signal between a third voltage level and a fourth voltage level at the second output terminal based on the second oscillating signal and the switched voltage levels at the first output terminal. ### Claim 14 A voltage level shifter comprising: a first switching circuit having a first input terminal for receiving a first oscillating signal and a first output terminal, the first switching circuit for switching the first oscillating signal between a first voltage level and a second voltage level at the first output terminal; and a second switching circuit having a second input terminal connected to the first output terminal, a second output terminal, and a third input terminal for receiving a second oscillating signal, the second oscillating signal being out of phase with the first oscillating signal, the second switching circuit including a first transistor and a second transistor connected in series with the first transistor, the node between the two transistors defining the second output terminal, wherein the control terminals of the first and second transistors are connected to the first output terminal, the second switching circuit for switching the second oscillating signal between a third voltage level and a fourth voltage level at the second output terminal based on the second oscillating signal and the switched voltage levels at the first output terminal. ### Claim 15 A voltage level shifter comprising: an inverter having a first output terminal and a first input terminal for receiving a first oscillating signal; and a switching circuit having a second output terminal, a second input terminal connected to the first output terminal, and a third input terminal for receiving a second oscillating signal, the second oscillating signal being out of phase with the first oscillating signal, the switching circuit including a first transistor and a second transistor connected in series with the first transistor and defining the second output terminal there between wherein the gate terminals of the first and second transistors are connected to the first output terminal, the switching circuit for shifting the second oscillating signal between a first voltage level and a second voltage level at the second output terminal based on the second oscillating signal and the voltage level at the first output terminal. ### Claim 16 A voltage level shifter comprising: a first switching circuit having a first input terminal for receiving a first oscillating signal and a first output terminal, the first switching circuit for switching the first oscillating signal between a first voltage level and a second voltage level at the first output terminal; a second switching circuit having a second input terminal connected to the first output terminal, a second output terminal, and a third input terminal for receiving a second oscillating signal, the second oscillating signal being out of phase with the first oscillating signal, the second switching circuit for switching the second oscillating signal between a third voltage level and a fourth voltage level at the second output terminal based on the second oscillating signal and the switched voltage levels at the first output terminal; and the first switching circuit including a first switch and a second switch connected in series with each other, each having a control terminal coupled to the first input terminal. ### Claim 17 A voltage level shifter comprising: a first switching circuit having a first input terminal for receiving a first oscillating signal and a first output terminal, the first switching circuit for switching the first oscillating signal between a first voltage level and a second voltage level at the first output terminal; a second switching circuit having a second input terminal connected to the first output terminal, a second output terminal, and a third input terminal for receiving a second oscillating signal, the second oscillating signal being out of phase with the first oscillating signal, the second switching circuit for switching the second oscillating signal between a third voltage level and a fourth voltage level at the second output terminal based on the second oscillating signal and the switched voltage levels at the first output terminal; and the second switching circuit including a first transistor and a second transistor connected in series with the first transistor, the node between the two transistors defining the second output terminal, the control terminals of the first and second transistors being connected to the first output terminal. ### Claim 18 (depends on 17) The shifter according to claim 17 wherein the second switching circuit further includes: a third transistor connected in series with the first transistor; and a fourth transistor connected in series with the second transistor, wherein the control terminals of the third and fourth transistors are coupled to the third input terminal. ### Claim 19 A voltage level shifter comprising: an inverter having a first output terminal and a first input terminal for receiving a first oscillating signal; a switching circuit having a second output terminal, a second input terminal connected to the first output terminal, and a third input terminal for receiving a second oscillating signal, the second oscillating signal being out of phase with the first oscillating signal, the switching circuit for shifting the second oscillating signal between a first voltage level and a second voltage level at the second output terminal based on the second oscillating signal and the voltage level at the first output terminal; and the switching circuit including a first transistor and a second transistor connected in series with the first transistor and defining the second output terminal therebetween, the gate terminals of the first and second transistors being connected to the first output terminal. ### Claim 20 (depends on 19) The shifter of claim 19 wherein the switching circuit further includes: a pull-up transistor connected in series with the first transistor for shifting the voltage level at the second output terminal to the first voltage level; and a pull-down transistor connected in series with the second transistor for shifting the voltage level at the second output terminal to the second voltage level, wherein the gate terminals of the pull-up and pull-down transistors are coupled to the third input terminal.