# US 5,705,942 A · Method and apparatus for locating and improving critical speed paths in VLSI integrated circuits

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- Number: US 5,705,942 A
- Document ID: US5705942A
- Status: Granted
- Kind: A
- Application number: 08/537,092
- Filed: 1995-09-29
- Granted: 1998-01-06
- Earliest claimed: 1995-09-29
- Assignees: Intel Corporation
- Inventors: Roni Ashuri
- Web page: https://patentgrep.com/patent/US5705942A

## CPC

- H03K 5/131: Digitally controlled
- G01R 31/3016: {Delay or race condition test, e.g. race hazard test}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

An improved local clock driver for locating critical speed paths within a integrated digital circuit. Highly integrated digital circuits have many local circuits and each local circuit has a local clock driver. The local clock driver strengthens and distributes a clock signal within the local circuit. The improved local clock driver introduces a controllable delay circuit in all the local clock drivers of the digital integrated circuit. By selectively delaying each local clock driver, critical speed paths can be located. To compensate for critical speed paths, the delay circuit can be turned on in the receiving local block circuit.

## Claims

### Claim 1

A method of locating a critical speed path in an integrated circuit, said method comprising the steps of
increasing a clock speed of the integrated circuit until the integrated circuit fails;
delaying a local clock signal in a circuit subblock; and
testing said integrated circuit, if said integrated circuit functions properly then said circuit subblock is a destination subblock of said critical speed path, else delay a different local clock signal in a different circuit subblock and repeat said steps of delaying and testing until said integrated circuit functions properly.

### Claim 2 (depends on 1)

The method of locating a critical speed path in an integrated circuit as claimed in claim 1 further comprising the steps of
delaying said local clock signal in said destination subblock;
delaying a second local clock signal in a second circuit subblock; and
testing said integrated circuit, if said integrated circuit fails then said second circuit subblock is a source subblock of said critical speed path, else delay a different local clock signal in a different second circuit subblock and repeat said steps of delaying and testing until said integrated circuit fails.

### Claim 3

An integrated circuit, said integrated circuit comprising the elements of
a plurality of circuit subblocks, said circuit subblocks comprising different logic circuits;
a plurality of data paths, said data paths connecting said plurality of circuit subblocks, said data paths introducing propagation delay;
a plurality of serially coupled local clock drivers, wherein a local clock driver is coupled to each of said plurality of circuit subblocks, said local clock driver generating a local clock signal for synchronizing transmission along said data paths, said local clock driver having a programmable delay enable that allows a delay to be selectively introduced in said local clock signal.

### Claim 4 (depends on 3)

The integrated circuit as claimed in claim 3 wherein said programmable delay enable in each local clock driver toggles a switch coupled to a capacitor that is coupled to an electrical ground.

### Claim 5

A clocking circuit, said clocking circuit comprising the elements of
an advance input;
a plurality, of serially coupled clock driver circuits, wherein each clock driver circuit further comprises:
a driver circuit for generating a local clock signal;
a delay circuit coupled to said local clock signal, said delay circuit for delaying said local clock signal; and
a delay latch coupled to said delay circuit and said advance input, said delay latch for transmitting and latching delay signals along said serially coupled clock driver circuits; and
a first input, said first input coupled to a first clock driver circuit of said serially coupled clock driver circuits.

### Claim 6 (depends on 5)

The clock driver circuit as claimed in claim 5, wherein said delay circuit comprises a capacitor coupled to ground.

### Claim 7

A method of improving a critical speed path in an integrated circuit, said method comprising the steps of:
increasing a clock speed of the integrated circuit until the integrated circuit fails;
delaying a local clock signal in a circuit subblock; and
testing said integrated circuit, if said integrated circuit functions properly then said circuit subblock is said destination subblock of said critical speed path, else delaying a different local clock signal in a different circuit subblock and repeating said steps of delaying and testing until said integrated circuit functions properly; and
selectively delaying a local clock driver in said destination circuit of said critical speed path.

### Claim 8 (depends on 7)

The method of claim 7 wherein said step of selectively delaying a local clock driver in a destination circuit comprises adding capacitance to said local clock signal in said local clock driver.