# US 5,705,940 A · Logic family for digitally controlled analog monolithic microwave integrated circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,705,940 A - Document ID: US5705940A - Status: Granted - Kind: A - Application number: 07/553,938 - Filed: 1990-07-16 - Granted: 1998-01-06 - Earliest claimed: 1990-07-16 - Assignees: Raytheon Company - Inventors: Paul F. Newman; Steven C. Evangelista - Web page: https://patentgrep.com/patent/US5705940A ## CPC - H03K 19/0952: using Schottky type FET {MESFET}({H03K19/09421, H03K19/09432}, H03K19/096 take precedence) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A transmit/receive module including digitally controlled analog circuits is described. The digital circuits use a logic family adapted for use with analog monolithic integrated circuits. The disclosure also describes a preferred process to provide digital and analog microwave circuits on a common semiconductor substrate. ## Claims ### Claim 1 A digital logic gate comprising: a) a logic branch comprising: i) a first pair of metal semiconductor field effect transistors, each transistor having a gate electrode, a drain electrode, and a source electrode, with the drain electrode of a first one of said first pair of transistors coupled to a first potential, the source electrode of said first transistor coupled to the drain electrode of the second one of said transistors and the source electrode of said second transistors coupled to a second potential; and ii) means disposed in the logic branch for reducing nominal branch currents flowing in said logic branch; b) a buffer branch, comprising: i) a second pair of metal semiconductor field effect transistors, each transistor having a gate electrode, source electrode, and drain electrode, with a first one of said second pair of transistors having the gate electrode thereof coupled to the drain electrode of the second transistor in the logic branch, the drain electrode of said first transistor of said second pair of transistors being coupled to the first potential, and said second transistor having source electrodes coupled to a third potential; and ii) means coupled to the source electrode of the first transistor in the buffer branch and the drain electrode of the second transistor in the buffer branch for providing four forward voltage diode drops between the source electrode of the first transistor and the drain electrode of the second transistor; iii) means disposed in said buffer branch for reducing buffer branch currents flowing through said buffer branch; and c) an output branch comprising: i) an output transistor having a drain electrode coupled to the drain electrode of the second transistor of said second pair of transistors, and a source electrode coupled to the output terminal of the logic circuit; and ii) means disposed in said output branch for reducing nominal branch currents flowing through the output terminal of said digital logic gate. ### Claim 2 (depends on 1) The digital logic gate of claim 1 wherein each one of said means for reducing nominal branch currents includes a resistor. ### Claim 3 (depends on 2) The digital logic gate of claim 2 wherein said resistor of each one of said means is disposed between a source electrode of a corresponding transistor in a corresponding branch of said gate and the gate electrode of said corresponding transistor. ### Claim 4 (depends on 3) The logic gate of claim 3 wherein said means for providing four forward voltage diode drops comprises four diodes coupled in series between the first transistor and the second transistor of the output branch. ### Claim 5 (depends on 4) The digital logic gate of claim 4 wherein said logic gate is an inverter. ### Claim 6 (depends on 5) The digital logic gate of claim 5 further comprising: a third transistor disposed in said logic branch between the source electrode of the second one of the pair of transistors of a logic branch and the second potential and wherein said logic gate is a NAND gate. ### Claim 7 (depends on 5) The logic gate of claim 5 further comprising: a third transistor disposed in said logic branch between the connection of the drain electrode of the first transistor and the second potential and wherein said logic gate is a NOR gate. ### Claim 8 An output driver circuit comprising: a logic branch including a first pair of metal semiconductor field effect transistors, each one of said transistors having gate, drain, and source electrodes, with the drain electrodes of a first one of the transistors coupled to a first potential the source electrode of the first transistor coupled to the drain electrode of a second transistor, and the source electrode of a second transistor coupled to a reference potential; a pair of pull-down transistors, each one being a metal semiconductor field effect transistor having source, drain, and gate electrodes with each one of said transistors having a source electrode coupled to a reference potential; a third transistor having a drain electrode coupled to the drain electrode of a second one of the transistors in the logic branch, and the source electrode coupled to the gate electrodes of each one of said pull-down transistors; a pull-up transistor having a drain electrode coupled to a first potential, a source electrode coupled via a diode voltage drop to the drain electrode of a second one of said pull-down transistors; and means for providing a variable adjustable reference voltage coupled to the drain electrode of a first one of said pull-down transistors and the gate electrode of said pull-up transistor.