# US 5,705,937 A · Apparatus for programmable dynamic termination > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,705,937 A - Document ID: US5705937A - Status: Granted - Kind: A - Application number: 08/605,924 - Filed: 1996-02-23 - Granted: 1998-01-06 - Earliest claimed: 1996-02-23 - Assignees: Cypress Semiconductor Corporation - Inventors: Kok-Kean Yap - Web page: https://patentgrep.com/patent/US5705937A ## CPC - H03H 11/28: Impedance matching networks - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) ## Abstract The present invention provides a device for terminating a data bus. The present invention provides the proper termination without the use of external discrete components. The device can be programmed, at the chip level, to produce particular termination resistances that are commonly used. The present invention termination device uses a minimum of power dissipation which may be useful in applications that require minimum power consumption. ## Claims ### Claim 1 A device for terminating a data bus comprising: one or more termination elements each having (i) a load output, (ii) a bus input and (iii) a plurality of control inputs, each of said elements presents one of a plurality of resistances at each of said load outputs in response to said plurality of control inputs; and an input enable that is at either (i) a first digital state that enables said plurality of resistances or (ii) a second digital State that prevents any of said plurality of resistances from being presented at said load outputs. ### Claim 2 (depends on 1) The device according to claim 1 wherein said control inputs comprise a first control input and a second control input, wherein said first and second control inputs are used to determine which one of said plurality of resistances is presented at each of said load outputs. ### Claim 3 (depends on 1) The device according to claim 1 wherein: one of said resistances is configured to operate as a terminator of an Industry Standard Architecture (ISA) bus; and another one of said resistances is configured as a terminator of a Small Computer Systems Interface (SCSI) bus. ### Claim 4 (depends on 1) The device according to claim 1 further comprising an input/output terminal for providing an interface between said terminating device and an internal circuit. ### Claim 5 (depends on 1) The device according to claim 1 further comprising a bonding pad for providing an interface between said terminating device and an external device. ### Claim 6 (depends on 5) The device according to claim 5 further comprising: a plurality of transistors wherein at least two of said plurality of transistors provide a first resistance path and at least two of said plurality of transistors provide a second resistance path; a plurality of pass gates wherein at least one of said plurality of pass gates has a gate coupled to one of said plurality of control inputs to enable said first resistance path to produce one of said plurality of resistances; and another one of said plurality of pass gates has a gate coupled to another one of said plurality of control signals to enable said second resistance path to produce another one of said plurality of resistances. ### Claim 7 (depends on 6) The device according to claim 6 wherein each said plurality of pass gates is at a first state that enables said first or second resistance path or is at a second state that disables said first or second resistance path. ### Claim 8 (depends on 7) The device according to claim 7 wherein each of said plurality of pass gates switches between said first and second states in response to one of said plurality of control inputs. ### Claim 9 (depends on 6) The device according to claim 6 wherein each of said plurality of pass gates is at said first state when a first combination of said control inputs is present and is at a second state when a second combination of said control inputs is present. ### Claim 10 (depends on 6) The device according to claim 6 wherein said plurality of transistors are n-channel MOS transistors. ### Claim 11 (depends on 6) The device according to claim 6 wherein said plurality of pass gates are p-channel MOS pass gates. ### Claim 12 (depends on 6) The device according to claim 6 wherein said plurality of transistors are p-channel MOS transistors. ### Claim 13 A device for terminating a data bus comprising: one or more termination elements each having (i) a load output, (ii) a bus input and (iii) a plurality of control inputs, each of said elements presents one of a plurality of resistances at each of said load outputs in response to said plurality of control inputs; a plurality of transistors wherein at least two of said plurality of transistors provide a first resistance path and at least two of said plurality of transistors provide a second resistance path; a plurality of pass gates wherein at least one of said plurality of pass gates has a gate coupled to one of said plurality of control inputs to enable said first resistance path to produce one of said plurality of resistances; and another one of said plurality of pass gates has a gate coupled to another one of said plurality of control signals to enable said second resistance path to produce another one of said plurality of resistances. ### Claim 14 (depends on 13) The device according to claim 13 wherein each of said plurality of pass gates is at a first state that enables said first or second resistance path or is at a second state that disables said first or second resistance path. ### Claim 15 (depends on 14) The device according to claim 14 wherein each of said plurality of pass gates switches between said first and second states in response to one of said plurality of control inputs. ### Claim 16 (depends on 13) The device according to claim 13 wherein each of said plurality of pass gates is at said first state when a first combination of said control inputs is present and is at a second state when a second combination of said control inputs is present. ### Claim 17 The device according to claim, 13 wherein said plurality of transistors are n-channel MOS transistors. ### Claim 18 (depends on 13) The device according to claim 13 wherein said plurality of pass gates are p-channel MOS pass gates.