# US 5,705,857 A · Capped copper electrical interconnects

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- Number: US 5,705,857 A
- Document ID: US5705857A
- Status: Granted
- Kind: A
- Application number: 08/618,023
- Filed: 1996-03-25
- Granted: 1998-01-06
- Earliest claimed: 1995-05-12
- Assignees: International Business Machines Corporation
- Inventors: Mukta Shaji Farooq; Suryanarayana Kaja; Eric Daniel Perfecto; George Eugene White
- Web page: https://patentgrep.com/patent/US5705857A

## CPC

- H05K 3/108: {by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241)}
- H10W 20/4421: {the principal metal being copper}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/66: Conductive materials thereof
- H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass}
- H05K 3/062: {consisting of metals or alloys or metallic inorganic compounds (H05K3/065 takes precedence)}
- H05K 3/388: {by the use of a metallic or inorganic thin film adhesion layer}
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H05K 2203/0597: Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
- H05K 2203/1105: Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

## Claims

### Claim 1

A capped electrical interconnect structure comprising a substrate, having at least one first seed layer, at least one second seed layer over said at least one first seed layer, a copper material on a portion of said at least one second seed layer and at least one capping material which completely envelopes said copper material, wherein a peripheral edge portion of said at least one capping material makes direct electrical contact with a portion of the upper surface of said at least one second seed layer and wherein the side walls of said at least one first seed layer and said at least one second seed layer do not have any capping material, and, wherein the total thickness of said at least one first seed layer and said at least one second seed layer is at least about 0.05 micron, and wherein material for said at least one first seed layer is different than material for said at least one second seed layer, and wherein at least a portion of said substrate is selected from a group consisting of ceramic substrate or glass ceramic substrate.

### Claim 2

A capped electrical interconnect structure comprising a substrate, having at least one first seed layer, at least one second seed layer over said at least one first seed layer, a copper material on a portion of said at least one second seed layer and at least one capping material which completely envelopes said copper material, wherein a peripheral edge portion of said at least one capping material makes direct electrical contact with a portion of the upper surface of said at least one second seed layer and wherein the side walls of said at least one first seed layer and said at least one second seed layer do not have any capping material, and, wherein the thickness of said copper material is between about 0.5 micron and about 100.0 microns, and wherein at least a portion of said substrate is selected from a group consisting of ceramic substrate or glass ceramic substrate.

### Claim 3

A capped electrical interconnect structure comprising a substrate, having at least one first seed layer, at least one second seed layer over said at least one first seed layer, a copper material on a portion of said at least one second seed layer and at least one capping material which completely envelopes said copper material, wherein a peripheral edge portion of said at least one capping material makes direct electrical contact with a portion of the upper surface of said at least one second seed layer and wherein the side walls of said at least one first seed layer and said at least one second seed layer do not have any capping material, and, wherein the thickness of said capping layer is between about 0.005 micron and about 10.000 microns, and wherein at least a portion of said substrate is selected from a group consisting of ceramic substrate or glass ceramic substrate.

### Claim 4

A capped electrical interconnect structure comprising a substrate, having at least one first seed layer, at least one second seed layer over said at least one first seed layer, a copper material on a portion of said at least one second seed layer and at least one capping material which completely envelopes said copper material, wherein a peripheral edge portion of said at least one capping material makes direct electrical contact with a portion of the upper surface of said at least one second seed layer and wherein the side walls of said at least one first seed layer and said at least one second seed layer do not have any capping material, and, wherein the total thickness of said at least one first seed layer and said at least one second seed layer is at least about 0.05 micron, and wherein material for said at least one first seed layer is different than material for said at least one second seed layer, and wherein material for said at least one first seed layer is selected from a group consisting of chromium, titanium, titanium-tungsten or alloys thereof.

### Claim 5

A capped electrical interconnect structure comprising a substrate, having at least one first seed layer, at least one second seed layer over said at least one first seed layer, a copper material on a portion of said at least one second seed layer and at least one capping material which completely envelopes said copper material, wherein a peripheral edge portion of said at least one capping material makes direct electrical contact with a portion of the upper surface of said at least one second seed layer and wherein the side walls of said at least one first seed layer and said at least one second seed layer do not have any capping material, and, wherein the total thickness of said at least one first seed layer and said at least one second seed layer is at least about 0.05 micron, and wherein material for said at least one first seed layer is different than material for said at least one second seed layer, and wherein material for said at least one second seed layer is selected from a group consisting of aluminum, copper or alloys thereof.