# US 5,705,842 A · Horizontal MOSFET > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,705,842 A - Document ID: US5705842A - Status: Granted - Kind: A - Application number: 08/813,102 - Filed: 1997-03-07 - Granted: 1998-01-06 - Earliest claimed: 1994-03-08 - Assignees: Fuji Electric Co., Ltd. - Inventors: Akio Kitamura; Naoto Fujishima - Web page: https://patentgrep.com/patent/US5705842A ## CPC - H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] - H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A horizontal MOSFET prevents itself from breakdown caused by an avalanche current which flows to a base of a parasitic bipolar transistor when avalanche breakdown of a diode formed between a drain and a substrate occurs. A current path, comprised of a back electrode or a layer with high impurity concentration, is disposed on the side of a back surface of a semiconductor substrate. This current path reduces the base current of the parasitic transistor. Due to this, heat generation caused by an operation of the parasitic transistor is suppressed, and the avalanche withstand capability of the MOSFET is improved corresponding to reduction of the internal resistance component of the MOSFET. ## Claims ### Claim 1 A horizontal MOSFET comprising: a semiconductor substrate of a first conductivity type; a well region of a second conductivity type formed from a first surface of the semiconductor substrate; base regions of the first conductivity type formed on a first side in a surface layer of the well region; a drain region of the second conductivity type formed on a second side of the surface layer of the well region; source regions of the second conductivity type selectively formed in surface layers of the base regions; a gate electrode disposed on a gate oxide film located on a surface of a region extending from the source regions to an exposed surface area of the well region; a drain electrode contacting with the drain region; a source electrode contacting commonly with the source regions and the base regions; a substrate electrode contacting with an exposed area of the semiconductor substrate exposed on a side of the source electrode far from the drain electrode and outside of the well region; and a current path of low resistance, including an electrode layer formed on a side of a second surface of the semiconductor substrate, through which an avalanche current flows, thereby increasing a breakdown characteristic of the horizontal MOSFET. ### Claim 2 (depends on 1) The horizontal MOSFET as claimed in claim 1, wherein the electrode layer is in ohmic contact with the second surface of the semiconductor substrate. ### Claim 3 (depends on 1) The horizontal MOSFET as claimed in claim 1, wherein the electrode layer forms a Schottky junction with the second surface of the semiconductor substrate. ### Claim 4 A horizontal MOSFET comprising: a semiconductor substrate of a first conductivity type; a well region of a second conductivity type formed from a first surface of the semiconductor substrate; base regions of the first conductivity type formed on a first side in a surface layer of the well region; a drain region of the second conductivity type formed on a second side of the surface layer of the well region; source regions of the second conductivity type selectively formed in surface layers of the base regions; a gate electrode disposed through gate oxide film on a surface of a region extending from the source regions to an exposed surface area of the well region; a drain electrode contacting with the drain region; a source electrode contacting commonly with the source regions and the base regions; a substrate electrode contacting with an exposed area of the semiconductor substrate exposed on a side of the source electrode far from the drain electrode; and a current path of low resistance formed on a side of a second surface of the semiconductor substrate; wherein the current path comprises a layer with high impurity concentration formed in a surface layer of the second surface of the semiconductor substrate. ### Claim 5 (depends on 1) The horizontal MOSFET as claimed claim 1, wherein the semiconductor substrate is 350 .mu.m or less in thickness. ### Claim 6 (depends on 2) The horizontal MOSFET as claimed claim 2, wherein the semiconductor substrate is 350 .mu.m or less in thickness. ### Claim 7 (depends on 3) The horizontal MOSFET as claimed claim 3, wherein the semiconductor substrate is 350 .mu.m or less in thickness. ### Claim 8 (depends on 4) The horizontal MOSFET as claimed claim 4, wherein the semiconductor substrate is 350 .mu.m or less in thickness. ### Claim 9 A horizontal MOSFET comprising: a semiconductor substrate of a first conductivity type; a well region of a second conductivity type formed from a first surface of the semiconductor substrate; base regions of the first conductivity type formed on a first side in a surface layer of the well region; a drain region of the second conductivity type formed on a second side of the surface layer of the well region; source regions of the second conductivity type selectively formed in surface layers of the base regions; a gate electrode disposed through gate oxide film on a surface of a region extending from the source regions to an exposed surface area of the well region; a drain electrode contacting with the drain region; a source electrode contacting commonly with the source regions and the base regions; a substrate electrode contacting with an exposed area of the semiconductor substrate exposed on a side of the source electrode far from the drain electrode; and a current path of low resistance formed on a side of a second surface of the semiconductor substrate; wherein the current path comprises an electrode layer which is in ohmic contact with the second surface of the semiconductor substrate; and wherein resistivity of the semiconductor substrate is 200 .OMEGA.cm or more, and a thickness thereof is thin enough to induce punch through by application of voltage corresponding to a reverse withstand voltage required for a PN junction between the drain region and the semiconductor substrate. ### Claim 10 (depends on 9) The horizontal MOSFET as claimed in claim 9, wherein the semiconductor substrate is 350 .mu.m or less in thickness. ### Claim 11 A horizontal MOSFET comprising: a semiconductor substrate of a first conductivity type; a well region of a second conductivity type formed from a first surface of the semiconductor substrate; base regions of the first conductivity type formed on a first side in a surface layer of the well region; a drain region of the second conductivity type formed on a second side of the surface layer of the well region; source regions of the second conductivity type selectively formed in surface layers of the base regions; a gate electrode disposed through gate oxide film on a surface of a region extending from the source regions to an exposed surface area of the well region; a drain electrode contacting with the drain region; a source electrode contacting commonly with the source regions and the base regions; a substrate electrode contacting with an exposed area of the semiconductor substrate exposed on a side of the source electrode far from the drain electrode; and a current path of low resistance formed on a side of a second surface of the semiconductor substrate; wherein the current path comprises an electrode layer which forms a Schottky junction with the second surface of the semiconductor substrate; and wherein resistivity of the semiconductor substrate is 200 .OMEGA.cm or more, and a thickness thereof is thin enough to induce punch through by application of voltage corresponding to a reverse withstand voltage required for a PN junction between the drain region and the semiconductor substrate. ### Claim 12 (depends on 11) The horizontal MOSFET as claimed in claim 11, wherein the semiconductor substrate is 350 .mu.m or less in thickness.