# US 5,705,841 A · Electrostatic discharge protection device for integrated circuits and its method for fabrication

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- Number: US 5,705,841 A
- Document ID: US5705841A
- Status: Granted
- Kind: A
- Application number: 08/851,808
- Filed: 1997-05-06
- Granted: 1998-01-06
- Earliest claimed: 1995-12-22
- Assignees: Winbond Electronics Corp.
- Inventors: Ta-Lee Yu
- Web page: https://patentgrep.com/patent/US5705841A

## CPC

- H10D 89/811: {using FETs as protective elements}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An electrostatic discharge (ESD) protection device includes a drain region and a source region, each having a heavily-doped region and a lightly-doped region, wherein the junction depth of the lightly-doped region is deeper than that of the heavily doped region. Accordingly, the ESD current density will be decreased owing to the enlarged junction area during the ESD event. In addition, the heat dissipation can be spread over the enlarged junction area instead of being focused on the cylindrical portion. Moreover, low parasitic capacitance in the bond pad is achieved because the junction capacitance of the lightly-doped region is smaller than that of the heavily-doped region. Furthermore, conducting blocks are arranged between the lightly-doped regions and the source/drain electrodes, respectively, to prevent the metal melt filament from spiking the junction.

## Claims

### Claim 1

An electrostatic discharge device, comprising:
a semiconductor substrate;
an isolating structure formed on said substrate;
a drain region and a source region formed in said substrate beneath opposite sides of said isolating structure, each of which is composed of a heavily-doped region and a lightly-doped region wherein said lightly-doped region has a junction depth greater than said heavily-doped region;
a first conducting block formed above and physically connecting directly to the lightly-doped region in said drain region;
a second conducting block formed above and physically connecting directly to the lightly-doped region in said source region;
a dielectric layer covering said isolating structure, source region, and drain region, first conducting block, and second conducting block, having a first contact window and a second contact window therethrough to expose said first conducting block and second conducting block, respectively;
a first electrode formed on said dielectric layer and coupled to said first conducting block via said first contact window; and
a second electrode formed on said dielectric layer and coupled to said second conducting block via said second contact window.

### Claim 2 (depends on 1)

The device as claimed in claim 1, wherein said isolating structure is a field oxide formed by a process of local oxidation of silicon (LOCOS).

### Claim 3 (depends on 1)

The device as claimed in claim 1, wherein each said lightly-doped region has a junction depth in a range between about 0.5 .mu.m-0.7 .mu.m, and a doping concentration in a range between about 5.times.10.sup.17 cm.sup.-3 -5.times.10.sup.18 cm.sup.-3.

### Claim 4 (depends on 3)

The device as claimed in claim 3, wherein each said heavily-doped region has a junction depth in a range between about 0.1 .mu.m-0.3 .mu.m, and a doping concentration in a range between about 5.times.10.sup.19 cm.sup.-3 -5.times.10.sup.20 cm.sup.-3.

### Claim 5 (depends on 1)

The device as claimed in claim 1, wherein said first electrode strides across said isolating structure.

### Claim 6 (depends on 1)

The device as claimed in claim 1, wherein said first electrode is connected to a bond pad.

### Claim 7 (depends on 1)

The device as claimed in claim 1, wherein said second electrode is connected to the ground.

### Claim 8

A method for fabricating an electrostatic discharge protection device, comprising:
providing a semiconductor substrate;
forming a field oxide layer on said substrate;
forming a diffusion barrier on said substrate not covered by said field oxide layer;
forming two openings through said diffusion barrier on opposite sides of said field oxide layer;
forming a polysilicon layer on said barrier layer to contact said substrate via said openings, wherein said polysilicon layer is doped with impurities;
diffusing said impurities, into said substrate to form two lightly-doped regions under said openings, respectively;
patterning said polysilicon layer to form two conducting blocks on said lightly-doped regions, respectively;
implanting ions into said substrate not covered by said field oxide layer and said conducting blocks to form heavily-doped regions, which have junction depths less than that of said lightly-doped regions;
forming a dielectric layer overlying the overall surface of said device;
forming two contact windows through said dielectric layer, each window exposing one of said conducting blocks; and
forming two electrodes, each electrode connected to one of said conducting blocks via a respective one of said contact windows.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein each said lightly-doped region has a junction depth in a range between about 0.5 .mu.m-0.7 .mu.m, and a doping concentration in a range between about 5.times.10.sup.17 cm.sup.-3 -5.times.10.sup.18 cm.sup.-3.

### Claim 10 (depends on 9)

The method as claimed in claim 9, wherein each said heavily-doped region has a junction depth in a range between about 0.1 .mu.m-0.3 .mu.m, and a doping concentration in a range between about 5.times.10.sup.19 cm.sup.-3 -5.times.10.sup.20 cm.sup.-3.

### Claim 11 (depends on 8)

The method as claimed in claim 8, wherein said semiconductor substrate is an N-type silicon substrate.

### Claim 12 (depends on 11)

The method as claimed in claim 11, wherein said impurities doped in said polysilicon contain phosphorus.

### Claim 13 (depends on 8)

The method as claimed in claim 8, wherein said diffusion barrier comprises a thin oxide layer and a thin polysilicon layer.

### Claim 14 (depends on 8)

The method as claimed in claim 8, wherein one of said electrode strides across said field oxide layer.

### Claim 15

The method as claimed in claim, 14, wherein said one electrode is connected to a bond pad.

### Claim 16 (depends on 15)

The method as claimed in claim 15, wherein the other of said electrodes is connected to ground.