# US 5,705,438 A · Method for manufacturing stacked dynamic random access memories using reduced photoresist masking steps > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,705,438 A - Document ID: US5705438A - Status: Granted - Kind: A - Application number: 08/735,061 - Filed: 1996-10-18 - Granted: 1998-01-06 - Earliest claimed: 1996-10-18 - Assignees: Vanguard International Semiconductor Corporation - Inventors: Horng-Huei Tseng - Web page: https://patentgrep.com/patent/US5705438A ## CPC - H10B 12/033: {the capacitor extending over the transistor} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A method for manufacturing stacked dynamic random access memory using reduced photomask steps was achieved. The invention utilizes two masking steps for forming the array of stacked capacitors and bit line contacts. One of the masking steps is used to concurrently form the bit line contact openings and to define the capacitor top electrode area for the stacked capacitors. After forming the array of field effect transistors by conventional means, an array of capacitor bottom electrodes is patterned from an N.sup.+ doped polysilicon layer using the first photoresist mask and plasma etching. An interelectrode dielectric layer is formed on the bottom electrodes. An N.sup.+ doped second poly-silicon layer and insulating layer are deposited. The insulating layer and second polysilicon layer are patterned with a second photoresist mask and plasma etched to concurrently form the bit line contact openings and to define the capacitor top electrode plate. The sidewalls of the exposed second polysilicon layer in the bit line contact openings are then oxidized to prevent the top electrode plate from shorting to the bit lines which are then patterned from a polycide layer that extends over and in the bit line contact openings. ## Claims ### Claim 1 A method for manufacturing stacked capacitors and bit lines for an array of dynamic random access memory (DRAM) cells on a semiconductor substrate comprising the steps of: providing a semiconductor substrate having device areas surrounded and electrically isolated from each other by field oxide areas; providing field effect transistors (FETs) in said device areas, each of said transistors having a gate electrode formed from a patterned first polysilicon layer, and having first and second source/drain contact areas in said device areas, and electrically insulated by depositing a conformal first insulating layer thereon; photoresist masking and anisotropically etching contact openings to said first source/drain contact areas of each said FET, thereby forming node contact openings for said stacked capacitors; depositing a conformal second poly-silicon layer on said substrate; patterning said second polysilicon layer using a first photoresist mask and anisotropic plasma etching leaving portions of said second polysilicon layer over and in said first source/drain contact areas thereby forming bottom electrodes for said stacked capacitors; forming a conformal second insulating layer on said patterned second polysilicon layer thereby forming an interelectrode dielectric layer on said bottom electrodes; depositing a conformal third polysilicon layer over said second insulating layer and elsewhere on said first insulating layer; depositing a third insulating layer on said third polysilicon layer; etching bit line contact openings using a second photoresist mask and anisotropic plasma etching over said second source/drain contact areas of each said FET through said third insulating layer and said third polysilicon layer to the surface of said first insulating layer; forming a thermal oxide on sidewalls of said third polysilicon layer exposed in said bit line contact openings; blanket etching and removing said first insulating layer in said bit line contact openings to said second source/drain contact areas of each said FET; depositing a conformal conducting layer on and in said second source/drain contact areas and elsewhere on said third insulating layer; patterning by photoresist masking and anisotropic plasma etching said conducting layer to form bit lines extending over said bit line contact openings thereby completing said array of DRAM cells having said stacked capacitors and bit lines. ### Claim 2 (depends on 1) The method of claim 1, wherein said first, second, and third poly-silicon layers are doped with N.sup.+ type electrically conducting dopant having a concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm.sup.3. ### Claim 3 (depends on 1) The method of claim 1, wherein said first polysilicon is between about 2500 and 3500 Angstroms thick. ### Claim 4 (depends on 1) The method of claim 1, wherein said first insulating layer is between about 600 and 1500 Angstroms thick. ### Claim 5 (depends on 1) The method of claim 1, wherein said second polysilicon layer is between about 3000 and 8000 Angstroms thick. ### Claim 6 (depends on 1) The method of claim 1, wherein said interelectrode dielectric layer is composed of silicon oxide-silicon nitride-silicon oxide (ONO) having a thickness of between about 10 and 100 Angstroms. ### Claim 7 (depends on 1) The method of claim 1, wherein said third polysilicon layer is between about 1000 and 2000 Angstroms thick. ### Claim 8 (depends on 1) The method of claim 1, wherein said third insulating layer is between about 4000 and 10000 Angstroms thick. ### Claim 9 (depends on 1) The method of claim 1, wherein said thermal oxide on said sidewalls of said third polysilicon layer electrically insulates said top electrodes from said bit lines, said thermal oxide grown to a thickness of between about 200 and 500 Angstroms. ### Claim 10 (depends on 1) The method of claim 1, wherein said conducting layer is a multilayer composed of an N.sup.+ doped polysilicon layer and a tungsten silicide layer. ### Claim 11 A method for manufacturing DRAM devices having arrays of stacked capacitors and bit lines on a semiconductor substrate comprising the steps of: providing a semiconductor substrate having device areas surrounded and electrically isolated from each other by field oxide areas; providing field effect transistors (FETs) in said device areas, each of said transistors having a gate electrode formed from a patterned first polysilicon layer, and having first and second source/drain contact areas in said device areas, and electrically insulated by depositing a conformal first insulating layer thereon; photoresist masking and anisotropically etching contact openings to said first source/drain contact areas of each said FET, thereby forming node contact openings for said stacked capacitors; depositing a conformal second poly-silicon layer on said substrate; patterning said second polysilicon layer using a first photoresist mask and anisotropic plasma etching leaving portions of said second poly-silicon layer over and in said first source/drain contact areas thereby forming bottom electrodes for said stacked capacitors; forming a conformal second insulating layer on said patterned second polysilicon layer thereby forming an interelectrode dielectric layer on said bottom electrodes; depositing a conformal third poly-silicon layer over said second insulating layer and elsewhere on said first insulating layer; depositing a third insulating layer on said third polysilicon layer; etching bit line contact openings using a second photoresist mask and anisotropic plasma etching over said second source/drain contact areas of each said FET through said third insulating layer and said third polysilicon layer to the surface said first insulating layer; forming a thermal oxide on sidewalls of said third polysilicon layer exposed in said bit line contact openings; blanket etching and removing said first insulating layer in said bit line contact openings to said second source/drain contact areas of each said FET; depositing a conformal fourth polysilicon/silicide layer on and in said second source/drain contact areas and elsewhere on said third insulating layer; patterning by photoresist masking and anisotropic plasma etching said poly-silicon/silicide layer to form bit lines extending over said bit line contact openings, and providing further processing to complete the wiring to the peripheral circuits on the DRAM chip thereby completing said DRAM device having said stacked capacitors and bit lines. ### Claim 12 (depends on 11) The method of claim 11, wherein said first, second, and third poly-silicon layers are doped with N.sup.+ type electrically conducting dopant having a concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm.sup.3. ### Claim 13 (depends on 11) The method of claim 11, wherein said first polysilicon is between about 2500 and 3500 Angstroms thick. ### Claim 14 (depends on 11) The method of claim 11, wherein said first insulating layer is between about 600 and 1500 Angstroms thick. ### Claim 15 (depends on 11) The method of claim 11, wherein said second polysilicon layer is between about 3000 and 8000 Angstroms thick. ### Claim 16 (depends on 11) The method of claim 11, wherein said inter-electrode dielectric layer is composed of silicon oxide-silicon nitride-silicon oxide (ONO). ### Claim 17 (depends on 16) The method of claim 16, wherein said interelectrode dielectric layer is between about 10 and 100 Angstroms thick. ### Claim 18 (depends on 11) The method of claim 11, wherein said third polysilicon layer is between about 1000 and 2000 Angstroms thick. ### Claim 19 (depends on 11) The method of claim 11, wherein said thermal oxide on said sidewalls of said third polysilicon layer electrically insulates said top electrodes from said bit lines, said thermal oxide grown to a thickness of between about 200 and 500 Angstroms. ### Claim 20 (depends on 11) The method of claim 11, wherein said fourth poly-silicon layer is N.sup.+ doped having a thickness of between about 1000 and 2000 Angstroms. ### Claim 21 (depends on 11) The method of claim 11, wherein said tungsten silicide layer is between about 1000 and 2000 Angstroms thick.