# US 5,705,436 A · Method for forming a poly load resistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,705,436 A - Document ID: US5705436A - Status: Granted - Kind: A - Application number: 08/703,085 - Filed: 1996-08-26 - Granted: 1998-01-06 - Earliest claimed: 1996-08-26 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Hsien Wei Chin; Jhon-Jhy Liaw - Web page: https://patentgrep.com/patent/US5705436A ## CPC - H10D 1/47: Resistors having no potential barriers - H10B 10/00: Static random access memory [SRAM] devices - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A physical implementation and method for achieving it are described for a load resistor and bus line subcircuit such as might be used in an SRAM cell. This was achieved by using two layers of polysilicon. The first polysilicon layer has low resistivity and serves to make effective contact to the drain regions of the FETs involved in the circuit. The second polysilicon layer has high resistivity and is used to form the load resistor as well as the collector bus line and resistor-drain connection. Formation of the latter two objects is achieved by providing a refractory metal underlay to the second polysilicon layer in the appropriate areas and then heating the structure so as to convert said refractory metal to its silicide. This process avoids the use of an ion implantation step during which some encroachment of the ions could occur, thereby retaining good control of the resistor dimensions. ## Claims ### Claim 1 A method for manufacturing a resistor and bus as parts of an integrated circuit, comprising: (a) providing a partially complete integrated circuit having a surface that includes contact regions; (b) depositing a first layer of polysilicon or polycide; (c) patterning and etching said first layer of polysilicon to form interconnections and electrodes for said contact regions; (d) depositing a layer of insulating material; (e) etching contact holes through said insulating layer down to the level of said first polysilicon layer; (f) depositing a layer of TiN; (g) patterning and etching said layer of TiN to fill said contact holes and to assume the shape of the bus; (h) depositing a second layer of polysilicon; (i) patterning and etching said second polysilicon layer to assume the shape of the resistor and to overlay said electrodes and said bus shaped area of TiN; and (j) heating said integrated circuit, thereby converting said layer of TiN to its silicide. ### Claim 2 (depends on 1) The method of claim 1 wherein the thickness of said first polysilicon or polycide layer is between about 2,000 and about 5,000 Angstroms. ### Claim 3 (depends on 1) The method of claim 1 wherein the sheet resistance of said first polysilicon or polycide layer is between about 10 and 30 ohm/sq. ### Claim 4 (depends on 1) The method of claim 1 wherein said insulating layer comprises silicon oxide. ### Claim 5 (depends on 1) The method of claim 1 wherein the thickness of said insulating layer is between about 1,000 and about 2,000 Angstroms. ### Claim 6 (depends on 1) The method of claim 1 wherein the thickness of said layer of TiN is between about 500 and about 2,000 Angstroms. ### Claim 7 (depends on 1) The method of claim 1 wherein the thickness of said second polysilicon layer is between about 500 and about 1,500 Angstroms. ### Claim 8 (depends on 1) The method of claim 1 wherein the sheet resistance of said second polysilicon layer is between about 1 and 1,000 megohm/sq. ### Claim 9 (depends on 1) The method of claim 1 wherein the integrated circuit is heated for between about 1 and about 20 minutes at a temperature between about 500.degree. and 700.degree. C. in an atmosphere of nitrogen. ### Claim 10 A method for manufacturing a resistor and bus as parts of an integrated circuit, comprising: (a) providing a partially complete integrated circuit having a surface that includes contact regions; (b) depositing a first layer of polysilicon or polycide; (c) patterning and etching said first layer of polysilicon to form interconnections and electrodes for said contact regions; (d) depositing a layer of insulating material; (e) etching contact holes through said insulating layer down to the level of said first polysilicon layer; (f) depositing a layer of TiW; (g) patterning and etching said layer of TiW to fill said contact holes and to assume the shape of the bus; (h) depositing a second layer of polysilicon; (i) patterning and etching said second polysilicon layer to assume the shape of the resistor and to overlay said electrodes and said bus shaped area of TiW; and (j) heating said integrated circuit, thereby converting said layer of TiW to its silicide. ### Claim 11 (depends on 10) The method of claim 10 wherein the thickness of said first polysilicon or polycide layer is between about 2,000 and about 5,000 Angstroms. ### Claim 12 (depends on 10) The method of claim 10 wherein the sheet resistance of said first polysilicon or polycide layer is between about 10 and 30 ohm/sq. ### Claim 13 (depends on 10) The method of claim 10 wherein said insulating layer comprises silicon oxide. ### Claim 14 (depends on 10) The method of claim 10 wherein the thickness of said insulating layer is between about 1,000 and about 2,000 Angstroms. ### Claim 15 (depends on 10) The method of claim 10 wherein the thickness of said TiW layer is between about 500 and about 2,000 Angstroms. ### Claim 16 (depends on 10) The method of claim 10 wherein the thickness of said second polysilicon layer is between about 500 and about 1,500 Angstroms. ### Claim 17 (depends on 10) The method of claim 10 wherein the sheet resistance of said second polysilicon layer is between about 1 and 1,000 megohm/sq. ### Claim 18 (depends on 10) The method of claim 10 wherein the integrated circuit is heated for between about 1 and about 20 minutes at a temperature between about 500.degree. and 700.degree. C. in an atmosphere of nitrogen.