# US 5,705,425 A · Process for manufacturing semiconductor devices separated by an air-bridge > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,705,425 A - Document ID: US5705425A - Status: Granted - Kind: A - Application number: 08/638,200 - Filed: 1996-04-26 - Granted: 1998-01-06 - Earliest claimed: 1992-05-28 - Assignees: Fujitsu Limited - Inventors: Takao Miura; Tunenori Yamauchi; Yoshinobu Monma; Hiroshi Goto - Web page: https://patentgrep.com/patent/US5705425A ## CPC - H10W 72/0198: {batch processes} - H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates - H10D 86/01: Manufacture or treatment - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 90/00: Package configurations - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/753: {between laterally-adjacent chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A process for manufacturing a semiconductor device comprising: a substrate having an insulating layer and a semiconductor layer lying on the insulating layer, the semiconductor layer having been divided to form a plurality of isolated semiconductor lands by trenches extending through the semiconductor layer to the insulating layer; integrated circuits formed on the respective lands; and conductors running above and across the trenches to electrically connect the integrated circuits on the isolated semiconductor lands. ## Claims ### Claim 1 A process of producing a semiconductor device, said process comprising the steps of: preparing a substrate having a first insulating layer and a semiconductor layer lying on the first insulating layer; forming a plurality of integrated circuits in the semiconductor layer; forming isolating trenches extending through the semiconductor layer to the first insulating layer so that the plurality of integrated circuits are separated and including regions filled with air, to form a plurality of isolated semiconductor lands mechanically connected to each other by the substrate, wherein side walls of said isolating trenches are covered with a diffused layer in the same conductivity type as that of the substrate; and electrically connecting the plurality of integrated circuits of the isolated semiconductor lands by conductors running above and across the regions of the isolating trenches filled with air after said step of forming isolating trenches. ### Claim 2 (depends on 1) A process according to claim 1, further comprising the steps of: forming a second insulating layer on the semiconductor layer; forming the isolating trenches extending from the second insulating layer to the first insulating layer; forming contact holes extending through the second insulating layer to the semiconductor layer; forming uppermost metal wiring layers on the second insulating layer and extending through ones of the contact holes to the semiconductor layer, the second insulating layer forming an interlayer insulating layer underlying the uppermost metal wiring layers; forming a protective insulating layer covering the uppermost metal wiring layers and the second insulating layer entirely; forming contact windows extending through the protective insulating layer to ones of the uppermost metal wiring layers; and electrically connecting the plurality of integrated circuits of the isolated semiconductor lands by the conductors via the contact windows. ### Claim 3 (depends on 1) A process according to claim 1, comprising the steps of: forming uppermost metal wiring layers of the plurality of integrated circuits, the uppermost wiring layers extending to the semiconductor layer; forming a first protective insulating layer on the uppermost metal wiring layers; forming the isolating trenches extending through the uppermost metal wiring layers to the first insulating layer; forming a second additional protective insulating layer covering the first protective insulating layer and the isolating trenches; forming contact windows extending through the second and first protective insulating layers to ones of the uppermost metal wiring layers; and electrically connecting the plurality of integrated circuits of the isolated semiconductor lands by the conductors via the contact windows. ### Claim 4 (depends on 1) A process according to claim 1, comprising the steps of: forming uppermost metal wiring layers of the plurality of integrated circuits, the uppermost metal wiring layer extending to the semiconductor layer; forming a first protective insulating layer on the uppermost metal wiring layers; forming contact holes extending through the first protective insulating layer to ones of the uppermost metal wiring layers; forming the isolating trenches extending through the first protective insulating layer to the first insulating layer; and electrically connecting the plurality of integrated circuits of the isolated semiconductor lands by the conductors via the contact windows. ### Claim 5 (depends on 1) A process according to claim 1, wherein the step of electrically connecting the plurality of integrated circuits is performed by wire bonding using a metal wire. ### Claim 6 (depends on 1) A process according to claim 1, wherein the step of electrically connecting the plurality of integrated circuits is performed by: preparing another substrate having a metal wiring layer formed thereon; forming metal pads on ones of the isolated semiconductor lands; preparing bumps; placing the bumps between the metal wiring layer and ones of the metal pads of the isolated semiconductor lands; and heating the substrate to fuse the bumps, thereby bonding the metal wiring layer to the ones of the metal pads through the fused bumps. ### Claim 7 (depends on 1) A process according to claim 1, further comprising the steps of: doping interland regions of the semiconductor layer with an impurity prior to forming the isolating trenches, the impurity being of the opposite conductivity type with respect to an impurity doped in active regions of electronic elements of the plurality of integrated circuits of the isolated semiconductor lands, wherein the electronic elements adjoin ones of the trenches, the interland regions being regions in which the isolating trenches are to be formed, to form the isolated semiconductor lands; and forming the isolating trenches in the interland regions, leaving the side walls of the isolating trenches doped with the impurity of the opposite conductivity type. ### Claim 8 (depends on 1) A process according to claim 1, wherein the substrate is a silicon-on-insulator substrate comprising the insulating layer, the semiconductor layer, and a lower semiconductor layer underlying the insulating layer. ### Claim 9 (depends on 1) A process according to claim 1, wherein the insulating layer of the substrate comprises one of glass and sapphire. ### Claim 10 (depends on 2) A process according to claim 2, wherein the step of electrically connecting the plurality of integrated circuits is performed by wire bonding using a metal wire. ### Claim 11 (depends on 3) A process according to claim 3, wherein the step of electrically connecting the plurality of integrated circuits is performed by wire bonding using a metal wire. ### Claim 12 (depends on 4) A process according to claim 4, wherein the step of electrically connecting the plurality of integrated circuits is performed by wire bonding using a metal wire. ### Claim 13 (depends on 2) A process according to claim 2, wherein the step of electrically connecting the plurality of integrated circuits is performed by: preparing another substrate having a metal wiring layer formed thereon; forming metal pads on ones of the isolated semiconductor lands; preparing bumps; placing the bumps between the metal wiring layer and ones of the metal pads of the isolated semiconductor lands; and heating the substrate to fuse the bumps, thereby bonding the metal wiring layer to the ones of the metal pads through the fused bumps. ### Claim 14 (depends on 3) A process according to claim 3, wherein the step of electrically connecting the plurality of integrated circuits is performed by: preparing another substrate having a metal wiring layer formed thereon; forming metal pads on ones of the isolated semiconductor lands; preparing bumps; placing the bumps between the metal wiring layer and ones of the metal pads of the isolated semiconductor lands; and heating the substrate to fuse the bumps, thereby bonding the metal wiring layer to the ones of the metal pads through the fused bumps. ### Claim 15 (depends on 4) A process according to claim 4, wherein the step of electrically connecting the plurality of integrated circuits is performed by: preparing another substrate having a metal wiring layer formed thereon; forming metal pads on ones of the isolated semiconductor lands; preparing bumps; placing the bumps between the metal wiring layer and ones of the metal pads of the isolated semiconductor lands; and heating the substrate to fuse the bumps, thereby bonding the metal wiring layer to the ones of the metal pads through the fused bumps. ### Claim 16 (depends on 2) A process according to claim 2, further comprising the steps of: doping interland regions of the semiconductor layer with an impurity prior to forming the isolating trenches, the impurity being of the opposite conductivity type with respect to an impurity doped in active regions of electronic elements of the plurality of integrated circuits of the isolated semiconductor lands, wherein the electronic elements adjoin ones of the trenches, the interland regions being regions in which the isolating trenches, are to be formed, to form the isolated semiconductor lands; and forming the isolating trenches in the interland regions, leaving the side walls of the trenches doped with the impurity of the opposite conductivity type. ### Claim 17 (depends on 3) A process according to claim 3, further comprising the steps of: doping interland regions of the semiconductor layer with an impurity prior to forming the isolating trenches, the impurity being of the opposite conductivity type with respect to an impurity doped in active regions of electronic elements of the plurality of integrated circuits of the isolated semiconductor lands, wherein the electronic elements adjoin ones of the trenches, the interland regions being regions in which the isolating trenches, are to be formed, to form the isolated semiconductor lands; and forming the isolating trenches in the interland regions, leaving the side walls of the trenches doped with the impurity of the opposite conductivity type. ### Claim 18 (depends on 4) A process according to claim 4, further comprising the steps of: doping interland regions of the semiconductor layer with an impurity prior to forming the isolating trenches, the impurity being of the opposite conductivity type with respect to an impurity doped in active regions of electronic elements of the plurality of integrated circuits of the isolated semiconductor lands, wherein the electronic elements adjoin ones of the trenches, the interland regions being regions in which the isolating trenches, are to be formed, to form the isolated semiconductor lands; and forming the isolating trenches in the interland regions, leaving the side walls of the trenches doped with the impurity of the opposite conductivity type. ### Claim 19 A process of producing a semiconductor device, said process comprising the steps of: preparing a substrate having an insulating layer and a semiconductor layer lying on the insulating layer; forming a plurality of integrated circuits in the semiconductor layer; forming isolating trenches through the semiconductor layer and down to the insulating layer, to separate the plurality of integrated circuits, the plurality of integrated circuits being mechanically connected to each other by the substrate, wherein side walls of said isolating trenches are covered with a diffused layer in the same conductivity type as that of the substrate; electrically connecting the separated plurality of integrated circuits with metal connectors running above and across the isolating trenches after said step of forming isolating trenches, wherein the isolating trenches have respective insulating spaces filled only with air.