# US 5,705,417 A · Method for forming self-aligned silicide structure

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- Number: US 5,705,417 A
- Document ID: US5705417A
- Status: Granted
- Kind: A
- Application number: 08/665,664
- Filed: 1996-06-19
- Granted: 1998-01-06
- Earliest claimed: 1996-06-19
- Assignees: Vanguard International Semiconductor Corporation
- Inventors: Horng-Huei Tseng
- Web page: https://patentgrep.com/patent/US5705417A

## CPC

- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- Y10S 148/147: Silicides
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

An improved method for forming a self-aligned silicide structure with reduced bridging effect is disclosed. The method includes forming a gate oxide on a substrate. Then a polysilicon layer is formed on the gate oxide. The polysilicon layer and the gate oxide are then patterned using a photoresist mask which defines a gate region. Next, the substrate is lightly-doped to form lightly-doped source/drain regions. Dielectric spacers are formed on a sidewall of the gate, and portions of the polysilicon layer and the substrate are removed with the dielectric spacers serving as a mask. A conductive layer is formed on the gate and the substrate, and is then silicided. Afterward, the unsilicided portions of the conductive layer are removed. Finally, heavily-doped source/drain regions are formed on the substrate with the dielectric spacers serving as a heavy-doping mask.

## Claims

### Claim 1

A method for forming a self-aligned silicide structure, said method comprising:
forming an oxide layer on a substrate;
forming a polysilicon layer on the oxide layer;
patterning the polysilicon layer and the oxide layer using a photoresist mask, wherein a gate region with a gate and gate oxide is formed;
doping the substrate to form lightly-doped source and drain regions using the gate as a doping mask;
forming a dielectric spacer on a sidewall of the gate;
removing a portion of the gate and removing portions of the substrate not covered by the dielectric spacer;
forming a conductive layer on the gate and the substrate;
reacting the conductive layer with portions of the gate and substrate to form a silicide;
removing portions of the conductive layer remaining after reacting the conductive layer with portions of the gate and substrate; and
forming heavily-doped source and drain regions by ion implantation using the dielectric spacer as an implant mask.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the thickness of said gate oxide is about 80 to 300 angstroms.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the thickness of said polysilicon layer is about 2000 to 4000 angstroms.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the oxide layer is deposited by low pressure chemical vapor deposition.

### Claim 5 (depends on 1)

The method according to claim 1, wherein said lightly-doped source and drain regions are formed by ion implantation.

### Claim 6 (depends on 1)

The method according to claim 1, wherein said dielectric spacer is about 1000 to 3000 angstroms wide.

### Claim 7 (depends on 1)

The method according to claim 1, wherein forming said dielectric spacer comprises:
forming a dielectric layer on the gate and the substrate; and
etching anisotropically the dielectric layer to form the dielectric spacer on the sidewall of the gate.

### Claim 8 (depends on 7)

The method according to claim 7, wherein said dielectric layer comprises a silicon oxide layer.

### Claim 9 (depends on 7)

The method according to claim 7, wherein said etching anisotropically the dielectric layer comprises reactive ion etching.

### Claim 10 (depends on 1)

The method according to claim 1, wherein said portions of the polysilicon and substrate are removed by a plasma etch process.

### Claim 11 (depends on 10)

The method according to claim 10, where the etchant of said plasma etch process is HBr/Cl.sub.2 /SF.sub.6.

### Claim 12 (depends on 1)

The method according to claim 1, wherein said conductive layer comprises a metal layer.

### Claim 13 (depends on 12)

The method according to claim 12, wherein said metal layer comprises a metal selected from the group of Pt, Pd, Co, Ni and Ti.

### Claim 14 (depends on 12)

The method according to claim 12, wherein said metal layer is formed on the gate and the substrate by sputter deposition.

### Claim 15 (depends on 1)

The method according to claim 1, wherein said conductive layer is reacted with portions of the gate and substrate using a temperature of about 600.degree. to 900.degree. C.

### Claim 16 (depends on 1)

The method according to claim 1, wherein said conductive layer is reacted with portions of the gate and substrate using a rapid thermal process.

### Claim 17 (depends on 1)

The method according to claim 1, wherein unreacted portions of the conductive layer are removed using an etchant of HCl:H.sub.2 O.sub.2 (about 30%) in a volume ration of about 3:1.

### Claim 18 (depends on 1)

The method according to claim 1, wherein said heavily-doped source and drain regions are formed by ion-implantation of dopants at a concentration of about 6.times.10.sup.15 ions/cm.sup.2 and an energy of about 60 KeV.

### Claim 19 (depends on 18)

The method according to claim 18, further comprising annealing the heavily-doped source and drain regions.

### Claim 20 (depends on 19)

The method according to claim 19, wherein said heavily-doped source and drain regions are annealed using a furnace.