# US 5,705,414 A · Method for producing a gate electrode for an MOS structure

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- Number: US 5,705,414 A
- Document ID: US5705414A
- Status: Granted
- Kind: A
- Application number: 08/779,944
- Filed: 1996-12-23
- Granted: 1998-01-06
- Earliest claimed: 1995-12-21
- Assignees: Siemens Aktiengesellschaft
- Inventors: Bernhard Lustig
- Web page: https://patentgrep.com/patent/US5705414A

## CPC

- H10D 64/01328: {by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall}
- Y10S 438/947: Subphotolithographic processing
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A gate electrode for an MOS structure, such as a short-channel MOS transistor, is produced. First, a hard mask is created, using a spacer of the material of the gate electrode as the etching mask, and the hard mask is used to structure the gate electrode. The method is suitable particularly for the production of gate electrodes with very thin gate dielectrics with channel lengths below 100 nm.

## Claims

### Claim 1

A method for producing a gate electrode for an MOS structure, which comprises:
forming an electrode layer of a given material on a gate dielectric formed on a semiconductor substrate;
applying an auxiliary layer on the electrode layer;
creating a step in the auxiliary layer such that a surface of the electrode layer remains covered by a step-structured auxiliary layer;
forming a spacer on the step from the given material;
anisotropically etching the step-structured auxiliary layer and forming a hard mask, using the spacer as an etching mask;
anisotropically etching the electrode layer and forming a gate electrode, using the hard mask as an etching mask; and
wherein the steps of forming the auxiliary layer, the spacer, the gate dielectric, and the electrode layer are performed using only two layer materials.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the step of forming the spacer comprises depositing a layer with conformal edge coverage and subsequently anisotropically etching.

### Claim 3 (depends on 1)

The method according to claim 1, which comprises forming the auxiliary layer and the gate dielectric of SiO.sub.2, and wherein the given material of the electrode layer and the spacer is polysilicon.