# US 5,705,320 A · Recovery of alignment marks and laser marks after chemical-mechanical-polishing

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- Number: US 5,705,320 A
- Document ID: US5705320A
- Status: Granted
- Kind: A
- Application number: 08/747,502
- Filed: 1996-11-12
- Granted: 1998-01-06
- Earliest claimed: 1996-11-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shun-Liang Hsu; Shih-Shiung Chen
- Web page: https://patentgrep.com/patent/US5705320A

## CPC

- G03F 7/70541: {Tagging, i.e. hardware or software tagging of features or components, e.g. using tagging scripts or tagging identifier codes for identification of chips, shots or wafers}
- G03F 7/70066: {Size and form of the illuminated area in the mask plane, e.g. reticle masking blades or blinds}
- G03F 7/70425: {Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning}
- G03F 7/70466: {Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature (stitching G03F7/70475)}
- G03F 9/00: Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically (G03F7/22 takes precedence; preparation of photographic masks G03F1/00; within photographic printing apparatus for making copies G03B27/00)
- G03F 9/70: {for microlithography (measuring printed patterns for monitoring overlay G03F7/70633 or focus G03F7/70641; projection system adjustment G03F7/70258; position control G03F7/70775)}
- G03F 9/7076: {Mark details, e.g. phase grating mark, temporary mark}
- H10W 46/201: {located on the periphery of wafers, e.g. orientation notches or lot numbers}
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The preservation of alignment marks and identification marks throughout the multitude of processing steps employed for the manufacture of integrated circuit chips often requires the inclusion of additional operations which impact production cost and product throughput. Current increased utilization of global planarization operations such as chemical-mechanical-polishing have forced the inclusion of additional window opening lithographic steps requiring additional masks and etch operations to keep these marks from being obscured. This invention provides a technique and a reticle design for clearing and preserving alignment and wafer identification marks through planarization and metallization levels with improved throughput and without the need for additional reticles to clear the marks. The alignment mark areas are exposed by a large clear-out window located in the frame area of the contact/via reticle while the wafer identification marks are accommodated in the same fashion by the metal pattern reticle. The lithography for integrated circuit pattern exposure and the window exposure is accomplished by a single stepper pass at each level.

## Claims

### Claim 1

A method for patterning a planarized insulative layer on a semiconductor wafer, said semiconductor wafer having a plurality of integrated circuit dice and a plurality of dice containing alignment marks, comprising:
(a) providing a semiconductor wafer having a plurality of integrated circuit dice and a plurality of dice containing alignment marks and having a planarized insulative layer over its surface;
(b) depositing a photoresist layer;
(c) mounting said semiconductor wafer on the stage of a stepper;
(d) mounting a reticle in said stepper, said reticle having a photolithographic image of an integrated circuit pattern enclosed within a rectangular frame region and a window in said frame region;
(e) aligning said semiconductor wafer to said alignment marks and exposing said photoresist layer over a first integrated circuit die with said photolithographic image;
(f) stepping and exposing said photoresist layer over said integrated circuit dice with said photolithographic image in sequence until a die containing said alignment marks is reached;
(h) making multiple overlapping exposures of said photoresist layer over said alignment marks through said window;
(l) repeating steps (f) through (h) until all said integrated circuit dice and all said dice containing alignment marks have been exposed;
(j) developing said photoresist layer; and
(k) etching said insulative layer with a unidirectional etching technique, thereby exposing said alignment marks.

### Claim 2 (depends on 1)

The method of claim 1 wherein said window is rectangular with dimensions of about 3.5 mm by 1.6 mm.

### Claim 3 (depends on 1)

The method of claim 1 wherein said integrated circuit pattern comprises contacts openings.

### Claim 4 (depends on 1)

The method of claim 1 wherein said integrated circuit pattern comprises via openings.

### Claim 5 (depends on 1)

The method of claim 1 wherein programmable mask blades are employed by said stepper during the performance of step (h) to expose said photoresist layer only through said window.

### Claim 6 (depends on 1)

The method of claim 1 wherein said unidirectional etching technique is reactive-ion-etching.

### Claim 7

A method for patterning an opaque layer deposited over a semiconductor wafer, said semiconductor wafer having a plurality of integrated circuit dice, a plurality of dice containing alignment marks, and a peripheral region containing identification marks, comprising:
(a) providing a semiconductor wafer having a plurality of integrated circuit dice, a plurality of dice containing alignment marks, and a peripheral region containing identification marks and having an opaque layer formed over its surface;
(b) depositing a photoresist layer;
(c) mounting said semiconductor wafer on the stage of a stepper;
(d) mounting a reticle in said stepper, said reticle having a rectangular photolithographic image of an integrated circuit pattern surrounded by a rectangular frame region and a window within said frame region;
(e) aligning and exposing a first integrated circuit die on said semiconductor wafer to said photolithographic image;
(f) stepping and exposing successive integrated circuit dice to said photolithographic image in sequence, skipping dies containing alignment marks until all integrated circuit dice have been exposed;
(g) stepping to said peripheral region;
(h) making multiple overlapping exposures through said window until said photoresist layer over said identification marks is exposed;
(l) developing said photoresist layer; and
(j) etching said opaque layer, thereby revealing said identification marks.

### Claim 8 (depends on 7)

The method of claim 7 wherein said window is rectangular with dimensions of about 3.5 mm by 1.6 mm.

### Claim 9 (depends on 7)

The method of claim 7 wherein said opaque layer is a metal.

### Claim 10 (depends on 7)

The method of claim 7 wherein said integrated circuit pattern comprises interconnection metallization.

### Claim 11 (depends on 7)

The method of claim 7 wherein programmable mask blades are employed by said stepper during the performance of step (h) to expose said photoresist layer only through said window.

### Claim 12 (depends on 7)

The method of claim 7 wherein said peripheral region is located adjacent to the flat edge of said semiconductor wafer.