# US 5,705,042 A · Electrically isolated collimator and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,705,042 A - Document ID: US5705042A - Status: Granted - Kind: A - Application number: 08/629,440 - Filed: 1996-04-08 - Granted: 1998-01-06 - Earliest claimed: 1996-01-29 - Assignees: Micron Technology, Inc. - Inventors: Shane P. Leiphart; Richard L. Elliot - Web page: https://patentgrep.com/patent/US5705042A ## CPC - H01J 37/32706: {Polarising the substrate} - C23C 14/046: {Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates} - C23C 14/34: Sputtering - H01J 37/34: operating with cathodic sputtering (H01J37/36 takes precedence {; methods of cathodic sputtering C23C14/34}) - H01J 37/3447: {Collimators, shutters, apertures} - H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H) - C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04) ## Abstract Disclosed is a collimator, where the collimator is mounted within a sputter chamber and is interposed between a sputter target and a wafer to be coated with a thin film of the sputtered material. The collimator of the present invention is preferably mounted within the sputter chamber in an insulated manner so that the collimator is electrically insulated from the chamber and the collimator is able to take on a floating electrical potential of the plasma generated within the sputter chamber. The wafer is preferably rf-biased to effectuate a selective, reduced-rate sputtering of portions of the deposited film to inhibit premature pinch off by the film of recessed areas of the wafer. ## Claims ### Claim 1 A sputter coating apparatus for sputter coating a semiconductor wafer, the apparatus comprising: an evacuable chamber; a sputter target mounted in said chamber; a semiconductor wafer support mounted in said chamber opposite said target for supporting said wafer; and a collimator interposed between the target and the semiconductor wafer support and mounted within the chamber in an electrically isolated manner so the collimator is able to take on a floating electrical potential within the chamber during plasma operations of the sputter coating apparatus in which the chamber is evacuated. ### Claim 2 A method of sputter deposition of a thin film on a semiconductor wafer in an evacuable chamber, the method comprising: mounting a sputter target in the chamber; mounting the wafer in the chamber opposite said target; interposing a collimator between the target and the wafer, and mounting the collimator within the chamber in an electrically isolated manner so the collimator takes on a floating electrical potential within the chamber during plasma operations in which the chamber is evacuated; creating a vacuum in the chamber; and generating a plasma within the chamber to cause the sputter deposition of a thin film of target material on the wafer. ### Claim 3 An apparatus for sputter deposition of a material on a semiconductor wafer, the apparatus comprising: a chamber adapted for creation of a vacuum therein and provided with a supply of an ionizable gas; a target of said material disposed in said chamber; a semiconductor wafer support disposed in said chamber spaced from said target; and a collimator interposed between said target and said wafer support and mounted within said chamber in an electrically isolated manner such that said collimator takes on a floating electrical potential within said chamber during plasma operations performed therein at vacuum. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein said wafer support is negatively-biased. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein said negative bias of said wafer support is achieved by an rf voltage. ### Claim 6 An apparatus for sputter deposition of a material on a semiconductor wafer, the apparatus comprising: a grounded chamber adapted for creation of a vacuum therein and provided with a supply of an ionizable gas; a negatively-biased target of said material disposed in said chamber; a negatively-biased semiconductor wafer support disposed in said chamber spaced from said target; and a collimator interposed between said target and said wafer support and mounted within said chamber in an electrically isolated manner such that said collimator takes on a floating electrical potential within said chamber during plasma operations performed therein at vacuum. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein said negative bias of said wafer support is achieved by an rf voltage. ### Claim 8 An apparatus for sputter deposition of a material on a semiconductor wafer, the apparatus comprising: a chamber adapted for creation of a vacuum therein, having at least a portion thereof at a first potential and provided with a supply of an ionizable gas; a target of said material at a second, different potential disposed in said chamber; a semiconductor wafer support disposed in said chamber spaced from said target; and a collimator electrically isolated from said chamber and from bias sources external to said chamber during plasma operations performed therein and interposed between said target and said wafer support. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein said second potential is more negative than said first potential. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein said wafer support is at a different potential from said first potential. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein said second potential is more negative than said first potential. ### Claim 12 A method for sputter deposition of a material on a semiconductor wafer, the method comprising: providing an evacuable chamber, at least a portion of which is at a first potential; providing a semiconductor wafer in the chamber; providing a source of said material for said deposition spaced from said wafer in said chamber; sputtering said material with a gas plasma resident in said chamber; providing a collimating apparatus within said chamber and collimating trajectories of sputtered material particles to features on the surface of said wafer with said collimating apparatus to form a film of said material on said wafer; and electrically isolating said collimating apparatus from said first potential and from bias sources external to said chamber during plasma operations performed within said chamber at vacuum. ### Claim 13 (depends on 12) The method of claim 12, further comprising maintaining said material source at a second potential different from said first potential, and maintaining said wafer at a third potential different from said first potential. ### Claim 14 (depends on 13) The method of claim 13, wherein said first potential comprises ground. ### Claim 15 A method for sputter deposition of a material on a semiconductor wafer including high aspect-ratio features on the surface thereof, the method comprising: providing an evacuable chamber having at least a portion thereof at a first potential; providing a wafer including said high aspect-ratio features within said chamber at a second potential different from said first potential; providing a source of said material for said deposition spaced from said wafer in said chamber; sputtering said material with a gas plasma resident in said chamber; providing a collimating apparatus within said chamber and collimating trajectories of sputtered material particles to features on the surface of said wafer with said collimating apparatus to form a film of said material on said wafer; electrically isolating said collimating apparatus from said first potential and from bias sources external to said chamber during plasma operations performed within said chamber at vacuum; and substantially reducing pinch off of said material proximate entry regions to said high aspect ratio features with said second potential. ### Claim 16 (depends on 15) The method of claim 15, wherein said pinch off is substantially reduced through sputtering of deposited material from said entry regions attributable to said second potential. ### Claim 17 (depends on 15) The method of claim 15, further including maintaining said gas plasma at a floating potential, and collimating said sputtered material particles at a potential associated with said floating potential of said gas plasma. ### Claim 18 A method for sputter deposition of a material on a semiconductor wafer including recesses in the surface thereof, comprising: providing a semiconductor wafer in an evacuable chamber; providing a source of said material for said deposition spaced from said wafer in said chamber; sputtering said material with a gas plasma resident in said chamber; maintaining said gas plasma at a floating electrical potential; providing a collimating apparatus within said chamber and collimating trajectories of sputtered material particles to features on the surface of said wafer with said collimating apparatus at a potential associated with said floating electrical potential of said gas plasma to form a film of said material on said wafer and within said recesses; and electrically isolating said collimating apparatus from said chamber and from bias sources external to said chamber during plasma operations performed within said chamber at vacuum. ### Claim 19 (depends on 18) The method of claim 18, further including maintaining said wafer at a potential different from said floating potential of said gas plasma, and sputtering portions of said material film from said wafer to enhance step coverage of said wafer. ### Claim 20 (depends on 19) The method of claim 19, further including achieving said enhanced step coverage by inhibiting pinch off at entry regions of recesses on said substrate. ### Claim 21 A method for sputter deposition of a target material on a semiconductor wafer, the method comprising: providing the target material and the wafer spaced apart from one another in a sputter deposition chamber; providing a collimator between the target material and the wafer in the chamber; electrically isolating the collimator from the chamber and any bias sources external to the chamber during plasma operations under vacuum within the chamber; evacuating the chamber; inducing a voltage differential between the chamber and the target material to generate a plasma within the chamber; bombarding the target material with ions from the plasma to dislodge material particles therefrom; collimating trajectories of the dislodged material particles to features on the wafer with the collimator to form a film of the target material on the wafer; operating the collimator at a floating electrical potential during sputter deposition so the plasma has more energy than if the collimator were operated at ground potential and so the plasma freely flows through the collimator; operating the chamber at a reduced pressure as a consequence of the collimator being operated at a floating electrical potential and the plasma thereby having relatively more energy; and biasing the wafer with a negative rf-voltage to substantially enhance the presence of the free-flowing plasma near the wafer and thereby reduce pinch-off of features on the wafer. ### Claim 22 A method for sputter deposition of a target material on a semiconductor wafer, the method comprising: providing the target material and the wafer spaced apart from one another in a sputter deposition chamber; generating a plasma within the chamber; bombarding the target material with ions from the plasma to dislodge material particles therefrom; at a floating electrical potential of the plasma, collimating trajectories of the dislodged material particles to features on the wafer to form a film of the target material on the wafer; and operating the chamber at a pressure that is less than a pressure the chamber would be operated at if trajectories of the dislodged material were collimated at an electrical potential of the chamber. ### Claim 23 A method for sputter deposition of a target material on a semiconductor wafer, the method comprising: providing the target material and the wafer spaced apart from one another in a sputter deposition chamber; generating a plasma within the chamber; bombarding the target material with ions from the plasma to dislodge material particles therefrom; at a floating electrical potential of the plasma, collimating trajectories of the dislodged material particles to features on the wafer to form a film of the target material on the wafer; and biasing the wafer to substantially enhance the presence of the plasma near the wafer.