# US 5,705,028 A · Method of manufacturing a semiconductor device with flattened multi-layer wirings

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- Number: US 5,705,028 A
- Document ID: US5705028A
- Status: Granted
- Kind: A
- Application number: 08/605,709
- Filed: 1996-02-22
- Granted: 1998-01-06
- Earliest claimed: 1993-04-21
- Assignees: Yamaha Corporation
- Inventors: Yasuhiko Matsumoto
- Web page: https://patentgrep.com/patent/US5705028A

## CPC

- H10P 95/06: {Planarisation of inorganic insulating materials}
- H10P 95/062: {involving a dielectric removal step}
- H10W 20/092: {by smoothing the dielectric parts}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A wiring layer formed on a field insulating film covering the surface of a semiconductor substrate is covered with an interlayer film. The interlayer film is covered with a flat film such as spin-on-glass formed by spin coating. The flat film has, for example, a laminated structure of an organic SOG film and an inorganic SOG film. The inorganic SOG film is suitable for obtaining a polishing speed generally equal to that of a CVD oxide film. The insulating film and the flat film are chemical-mechanical polished at a same polishing speed until the flat film is thoroughly removed, to leave a planarized insulating film.

## Claims

### Claim 1

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:
(a) providing a semiconductor substrate having a first level wiring structure thereon;
(b) forming a second level wiring structure on the first level wiring structure;
(c) forming an interlevel insulating film on the second level wiring structure, the interlevel insulating film having a corrugated surface, the interlevel insulating film directly contacting said second level wiring structure;
(d) forming a sacrificial film over the interlevel insulating film, said sacrificial film having non-conformal topography to the underlying interlevel insulating film to form a planar upper surface on the semiconductor device, wherein said forming the sacrificial film over the interlevel insulating film includes:
(d-1) forming a first sacrificial sublayer over the interlevel insulating film directly contacting said second level wiring structure, the first sacrificial sublayer including silanol-based organic spin-on-glass; and
(d-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sacrificial sublayers, the second sacrificial sublayer including inorganic spin-on-glass; and
(e) chemical-mechanical polishing the interlevel insulating film directly contacting said second level wiring structure and the sacrificial film to provide a planarized interlevel insulating film directly contacting said second level wiring structure.

### Claim 2

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:
(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure thereon;
(b) forming a first interlevel insulating film over the underlying structure having conformal topography to the underlying structure, said first interlevel insulating film directly contacting said underlying first level wiring structure;
(c) forming a first sacrificial film over the first insulating film, said first sacrificial film having non-conformal topography to the first insulating film and having a substantially planar upper surface, wherein said forming the first sacrificial film over the first insulating film includes:
(c-1) forming a first sacrificial sublayer over the first interlevel insulating film directly contacting said underlying first wiring structure, the first sacrificial sublayer including silanol-based organic spin-on-glass; and
(c-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial sublayer including inorganic spin-on-glass;
(d) chemical-mechanical polishing the first interlevel insulating film directly contacting said underlying first level wiring structure and the first sacrificial film to provide a planarized first interlevel insulating film directly contacting said underlying first level wiring structure;
(e) forming a second level wiring structure on the planarized first interlevel insulating film;
(f) forming a second interlevel insulating film over the second level wiring structure having conformal topography to the second level wiring structure, said second interlevel insulating film directly contacting said underlying second level wiring structure;
(g) forming a second sacrificial film over the second interlevel insulating film, said second sacrificial film having non-conformal topography to the second interlevel insulating film and having a substantially planar upper surface; and
(h) chemical-mechanical polishing the second interlevel insulating film directly contacting said underlying second level wiring structure and the second sacrificial film to provide a planarized second interlevel insulating film directly contacting said underlying second level wiring structure.

### Claim 3

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:
(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure thereon;
(b) forming a first interlevel insulating film over the underlying structure having conformal topography to the underlying structure, said first interlevel insulating film directly contacting said underlying first level wiring structure;
(c) forming a first sacrificial film over the first insulating film, said first sacrificial film having non-conformal topography to the first insulating film and having a substantially planar upper surface;
(d) chemical-mechanical polishing the first interlevel insulating film directly contacting said underlying first level wiring structure and the first sacrificial film to provide a planarized first interlevel insulating film directly contacting said underlying first level wiring structure:
(e) forming a second level wiring structure on the planarized first interlevel insulating film;
(f) forming a second interlevel insulating film over the second level wiring structure having conformal topography to the second level wiring structure, said second interlevel insulating film directly contacting said underlying second level wiring structure;
(g) forming a second sacrificial film Over the second interlevel insulating film, said second sacrificial film having non-conformal topography to the second interlevel insulating film and having a substantially planar upper surface, wherein said forming the second sacrificial film over the second interlevel insulating film includes:
(g-1) forming a first sacrificial sublayer over the second interlevel insulating film directly contacting said underlying second level wiring structure, the first sacrificial sublayer including silanol-based organic spin-on-glass; and
(g-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial sublayer including inorganic spin-on-glass; and
(h) chemical-mechanical polishing the second interlevel insulating film directly contacting said underlying second level wiring structure and the second sacrificial film to provide a planarized second interlevel insulating film directly contacting said underlying second level wiring structure.

### Claim 4

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:
(a) providing a semiconductor substrate having a first level wiring structure thereon;
(b) forming a second level wiring structure on the first level wiring structure;
(c) forming an interlevel insulating film on the second level wiring structure, the interlevel insulating film having a corrugated surface, the interlevel insulating film directly contacting said second level wiring structure;
(d) forming a sacrificial film over the interlevel insulating film, said sacrificial film having non-conformal topography to the underlying interlevel insulating film to form a planar upper surface on the semiconductor device, wherein said forming the sacrificial film over the interlevel insulating film includes:
(d-1) forming a first sacrificial sublayer over the interlevel insulating film directly contacting said second level wiring structure, the first sacrificial sublayer including inorganic spin-on-glass; and
(d-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sacrificial sublayers, the second sacrificial sublayer including silanol-based organic spin-on-glass; and
(e) chemical-mechanical polishing the interlevel insulating film directly contacting said second level wiring structure and the sacrificial film to provide a planarized interlevel insulating film directly contacting said second level wiring structure.

### Claim 5

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:
(a) providing a semiconductor substrate having a first level wiring structure thereon;
(b) forming a second level wiring structure having a first thickness on the first level wiring structure;
(c) forming an interlevel insulating film directly on the second level wiring structure, the interlevel insulating film having a second thickness thicker than said first thickness and having a corrugated surface having a convex portion having a first width and a concave portion having a second width wider than the first width;
(d) forming a sacrificial film over the interlevel insulating film having non-conformal topography to the underlying interlevel insulating film, the concave portion being filled with the sacrificial film, wherein said forming the sacrificial film over the interlevel insulating film includes:
(d-1) forming a first sacrificial sublayer over the interlevel insulating film, the first sacrificial sublayer including silanol-based organic spin-on-glass; and
(d-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sacrificial sublayers, the second sacrificial sublayer including inorganic spin-on-glass; and
(e) chemical-mechanical polishing the interlevel insulating film having said second thickness thicker than said first thickness and the sacrificial film to provide a planarized interlevel insulating film.

### Claim 6

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:
(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure having a first thickness thereon;
(b) forming a first interlevel insulating film directly over the underlying structure having conformal topography to the underlying structure, the first interlevel insulating film having a second thickness thicker than said first thickness and having a first convex portion having a first width and a first concave portion having a second width wider than the first width;
(c) forming a first sacrificial film over the first interlevel insulating film having non-conformal topography to the first interlevel insulating film, the first concave portion being filled with the first sacrificial film, wherein said forming the first sacrificial film over the first interlevel insulating film includes:
(c-1) forming a first sacrificial sublayer over the first interlevel insulating film, the first sacrificial layer including silanol-based organic spin-on-glass; and
(c-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial layer including inorganic spin-on-glass;
(d) chemical-mechanical polishing the first interlevel insulating film having a second thickness thicker than said first thickness and the first sacrificial film to provide a planarized first interlevel insulating film;
(e) forming a second level wiring structure having a third thickness on the planarized first insulating film;
(f) forming a second intelevel insulating film directly over the second level wiring structure having conformal topography to the second level wiring structure, the second interlevel insulating film having a fourth thickness thicker than said third thickness and having a second convex portion having a third width and a second concave portion having a fourth width wider than the third width;
(g) forming a second sacrificial film, having non-conformal topography to the second interlevel insulating film, the second concave portion being filled with the second sacrificial film; and
(h) chemical-mechanical polishing the second interlevel insulating film having said fourth thickness thicker than said third thickness and the second sacrificial film to provide a planarized second interlevel insulating film.

### Claim 7

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:
(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure having a first thickness thereon;
(b) forming a first interlevel insulating film directly over the underlying structure having conformal topography to the underlying structure, the first interlevel insulating film having a second thickness thicker than said first thickness and having a first convex portion having a first width and a first concave portion having a second width wider than the first width;
(c) forming a first sacrificial film over the first interlevel insulating film having non-conformal topography to the first interlevel insulating film, the first concave portion being filled with the first sacrificial film;
(d) chemical-mechanical polishing the first interlevel insulating film having a second thickness thicker than said first thickness and the first sacrificial film to provide a planarized first interlevel insulating film;
(e) forming a second level wiring structure having a third thickness on the planarized first insulating film;
(f) forming a second interlevel insulating film directly over the second level wiring structure having conformal topography to the second level wiring structure, the second interlevel insulating film having a fourth thickness thicker than said third thickness and having a second convex portion having a third width and a second concave portion having a fourth width wider than the third width;
(g) forming a second sacrificial film, having non-conformal topography to the second interlevel insulating film, the second concave portion being filled with the second sacrificial film, wherein said forming the second sacrificial film includes:
(g-1) forming a first sacrificial sublayer over the second interlevel insulating film, the first sacrificial sublayer including silanol-based organic spin-on-glass; and
(g-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial sublayer including inorganic spin-on-glass; and
(h) chemical-mechanical polishing the second interlevel insulating film having said fourth thickness thicker than said third thickness and the second sacrificial film to provide a planarized second interlevel insulating film.

### Claim 8

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:
(a) providing an underlying structure of a semiconductor substrate having an interconnection of wiring layers thereon;
(b) forming a first insulating film over the underlying structure having conformal topography to the underlying structure;
(c) forming a laminated sacrificial film having an upper surface and non-conformal topography to the first insulating film so that the upper surface of the laminated sacrificial film is planar, said laminated sacrificial film including a first sacrificial film of a first material formed over the interlevel insulating film and a second sacrificial film of a second material different from said first material formed over the first sacrificial film;
(d) chemical-mechanical polishing the first insulating film and the laminated sacrificial film to provide a planarized first insulating film; and
(e) depositing a layer of wiring material on the planarized first insulating film and then forming an upper wiring layer from the deposited layer of wiring material by use of photolithography.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first sacrificial film includes silanol-based organic spin-on-glass and the second sacrificial film includes inorganic spin-on-glass.

### Claim 10 (depends on 8)

The method of claim 8, wherein the second sacrificial film includes silanol-based organic spin-on-glass and the first sacrificial film includes inorganic spin-on-glass.

### Claim 11 (depends on 8)

The method of claim 8, wherein at the step (b), the first insulating film has convex topography and concave topography, and a width of said concave topography is larger than a width of said convex topography.

### Claim 12 (depends on 11)

The method of claim 11, wherein at the step (b), the first insulating film includes a material selected from the group consisting of BPSG, PSG, and SiO.sub.2 made through a plasma CVD technique.

### Claim 13 (depends on 8)

The method of claim 8, wherein at the step (d), the laminated sacrificial film is thoroughly removed.

### Claim 14

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:
(a) providing a semiconductor substrate having a first level wiring structure thereon;
(b) forming a second level wiring structure on the first level wiring structure;
(c) forming an interlevel insulating film on the second level wiring structure, the interlevel insulating film having a corrugated surface;
(d) forming a first sacrificial film of a first material over the interlevel insulating film;
(e) forming a second sacrificial film of a second material different from said first material over the first sacrificial film to provide a laminated structure of the first and second sacrificial films having non-conformal topography to the underlying interlevel insulating film to form a planar upper surface on the semiconductor device; and
(f) chemical-mechanical polishing the interlevel insulating film and the laminated structure of the first and second sacrificial films to provide a planarized interlevel insulating film.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first sacrificial film includes silanol-based organic spin-on-glass and the second sacrificial film includes inorganic spin-on-glass.

### Claim 16 (depends on 14)

The method of claim 14, wherein the second sacrificial film includes silanol-based organic spin-on-glass and the first sacrificial film includes inorganic spin-on-glass.

### Claim 17 (depends on 14)

The method of claim 14, wherein the first level wiring structure and the second level wiring structure include a material selected from the group consisting of aluminum, aluminum-silicon alloy, and aluminum-silicon-copper alloy.

### Claim 18 (depends on 14)

The method of claim 14, wherein the first level wiring structure and the second level wiring structure have a laminated structure of one of aluminum and aluminum alloy, and titanium.

### Claim 19 (depends on 14)

The method of claim 14, wherein at the step (c), the interlevel insulating film has convex topography and concave topography, and a width of said concave topography is larger than a width of said convex topography.

### Claim 20 (depends on 19)

The method of claim 19, wherein at the step (c), the interlevel insulating film includes a material selected from the group consisting of BPSG, PSG, and SiO.sub.2 made through a plasma CVD technique.

### Claim 21 (depends on 14)

The method of claim 14, wherein at the step (f), the laminated structure of the first and second sacrificial films is thoroughly removed.

### Claim 22

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:
(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure thereon;
(b) forming a first interlevel insulating film over the underlying structure having conformal topography to the underlying structure;
(c) forming a first sacrificial sublayer of a first material for a first sacrificial film over the first interlevel insulating film;
(d) forming a second sacrificial sublayer of a second material different from said first material for said first sacrificial film over the first sacrificial sublayer to provide a laminated structure of said first sacrificial film having non-conformal topography to the first insulating film and having a substantially planar upper surface;
(e) chemical-mechanical polishing the first interlevel insulating film and the laminated structure of the first sacrificial film to provide a planarized first interlevel insulating film;
(f) forming a second level wiring structure on the planarized first interlevel insulating film;
(g) forming a second interlevel insulating film over the second level wiring structure having conformal topography to the second level wiring structure;
(h) forming a third sacrificial sublayer of a third material for a second sacrificial film over the second interlevel insulating film;
(i) forming a fourth sacrificial sublayer of a fourth material different from said third material for said second sacrificial film over the third sacrificial sublayer to provide a laminated structure of said second sacrificial film having non-conformal topography to the second interlevel insulating film and having a substantially planar upper surface; and
(j) chemical-mechanical polishing the second interlevel insulating film and the laminated structure of the second sacrificial film to provide a planarized second interlevel insulating film.

### Claim 23 (depends on 22)

The method of claim 22, wherein the first sacrificial sublayer includes silanol-based organic spin-on-glass and the second sacrificial sublayer includes inorganic spin-on-glass.

### Claim 24 (depends on 22)

The method of claim 22, wherein the second sacrificial sublayer includes silanol-based organic spin-on-glass and the first sacrificial sublayer includes inorganic spin-on-glass.

### Claim 25 (depends on 22)

The method of claim 22, wherein at the step (e), the laminated structure of the first sacrificial film is thoroughly removed.

### Claim 26 (depends on 22)

The method of claim 22, wherein the third sacrificial sublayer includes silanol-based organic spin-on-glass and the fourth sacrificial sublayer includes inorganic spin-on-glass.

### Claim 27 (depends on 22)

The method of claim 22, wherein the fourth sacrificial sublayer includes silanol-based organic spin-on-glass and the third sacrificial sublayer includes inorganic spin-on-glass.

### Claim 28 (depends on 22)

The method of claim 22, wherein at the step (j), the laminated structure of the second sacrificial film is thoroughly removed.

### Claim 29

A surface planarizing method comprising the steps of:
(a) forming an insulating film on the surface of a substrate having a step;
(b) coating the insulating film with a laminated flat film having an upper surface and non-conformal topography to the insulating film so that the upper surface of the laminated flat film is planar, said laminated flat film including a first film of a first material formed over the insulating film and a second film of a second material different from said first material formed over the first film; and
(c) chemical-mechanical polishing the insulating film and the laminated flat film at a substantially similar material removal polishing speed for both the insulating film and the laminated flat film until the laminated flat film is thoroughly removed, to leave a planarized insulating film.

### Claim 30 (depends on 29)

The method of claim 29, wherein the first film includes silanol-based organic spin-on-glass and the second film includes inorganic spin-on-glass.

### Claim 31 (depends on 29)

The method of claim 29, wherein the second film includes silanol-based organic spin-on-glass and the first film includes inorganic spin-on-glass.