# US 5,704,058 A · Cache bus snoop protocol for optimized multiprocessor computer system

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- Number: US 5,704,058 A
- Document ID: US5704058A
- Status: Granted
- Kind: A
- Application number: 08/426,503
- Filed: 1995-04-21
- Granted: 1997-12-30
- Earliest claimed: 1995-04-21
- Inventors: John E. Derrick; Christopher M. Herring
- Web page: https://patentgrep.com/patent/US5704058A

## CPC

- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/0811: with multilevel cache hierarchies
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A cache bus snoop protocol optimizes performance of a multiprocessor computer system with multiple level two caches by allocating windows of cache bus snoop activity on a need basis. When a cycle to cacheable address space is requested, the cache bus is granted only after the necessary snoop and write-back cycles are completed. During the snoop and write-back cycles, snoop activity by other devices in inhibited.

## Claims

### Claim 1

A method of allocating windows of cache bus bandwidth for cache to cache and system snoop activity on a need basis to minimize impact on performance while maximizing memory page hit accesses comprising the steps of:
providing an address space having cacheable and non-cacheable portions;
providing a cycle request for access to a selected address within the address space;
determining from the selected address if the cycle request requires snoop activity by determining whether the selected address is in the cacheable address space;
allowing local bus and expansion bus activity to occur on the cache bus if the cycle request is for non-cacheable address space not requiring snoop activity; and
delaying the cycle request if snoop activity is required until it can be determined that the necessary snoop and write-back cycles can be completed.

### Claim 2 (depends on 1)

The method of claim 1 further including the step of inhibiting other devices from performing snoop cycles during the necessary snoop and write-back cycles.

### Claim 3 (depends on 2)

The method of claim 2 wherein the step of inhibiting other devices from performing snoop cycles comprises the step of providing a back off signal to the other devices that request a cycle during the necessary snoop and write-back cycles.