# US 5,704,052 A · Bit processing unit for performing complex logical operations within a single clock cycle > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,704,052 A - Document ID: US5704052A - Status: Granted - Kind: A - Application number: 08/635,541 - Filed: 1996-04-22 - Granted: 1997-12-30 - Earliest claimed: 1994-11-06 - Assignees: Unisys Corporation - Inventors: Gary C. Wu; Chandra S. Pawar; Steven H. Leibowitz; Edward J. Pullin; Michael J. Hazzard; Joseph C. Duggan - Web page: https://patentgrep.com/patent/US5704052A ## CPC - G06F 7/76: Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data - G06F 7/575: Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry - G06F 9/30018: {Bit or string instructions} - G06F 9/30038: {using a mask} - G06F 9/30094: {Condition code generation, e.g. Carry, Zero flag} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to perform the slow arithmetic operations (e.g., multiply, divide). The BPU has two special purpose registers, a zero flag and a match flag, which are used for program execution control. The BPU performs bit manipulations on data stored in and received from the register file and/or individual fields in the instruction currently being executed by the BPU. ## Claims ### Claim 1 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle. ### Claim 2 (depends on 1) The system of claim 1, wherein said bit processing unit has at least three inputs originating from said instruction register including a shift count field input, a literal field input, and a control field input. ### Claim 3 (depends on 1) The system of claim 1, wherein said bit processing unit includes a match flag that is updated by a compare bit operation and a zero flag that is set when said bit processing unit produces a result that is equal to zero. ### Claim 4 (depends on 1) The system of claim 1, wherein said shift functional unit having a first input connected to a literal field input representing a literal field of an instruction stored in said instruction register and a second input connected to a shift count input representing a shift count field of said instruction stored in said instruction register, and an output, said output representing the result of "a load literal field" operation that stores a value stored in said literal field of said instruction to a target field within a word, wherein bits outside said target field are cleared to zero. ### Claim 5 (depends on 1) The system of claim 1, wherein said specified number is contained in said instruction register. ### Claim 6 (depends on 1) The system of claim 1, wherein said specified number is contained in said register file. ### Claim 7 (depends on 1) The system of claim 1, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 8 A microprocessor for executing instructions within an instruction steam, comprising: instructions register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes: a shift functional unit having a first input and a second input connected to said instruction register and an output, and a NOT gate having an input connected to said output of said shift functional unit and an output, and an AND gate having a first input connected to said output of said NOT gate, a second input connected to said register file representing an input word, and an output, said output representing the result of a clear-bit field operation that resets specified bits of said input word to zero and leaves all other bits of said input word intact. ### Claim 9 (depends on 8) The system of claim 8, wherein said specified bits are determined based on a value contained in said instruction register. ### Claim 10 (depends on 8) The system of claim 8, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 11 A microprocessor for executing instructions with an instruction stream, comprising: an instruction register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes: a shift functional unit having a first input and a second input connected to said instruction register and an output, and an AND gate having a first input connected to said output of said shift functional unit, a second input connected to said register file representing an input word, and an output, said output representing the result of "an isolate bit-field" operation that resets all bits of said input word except specified bits of said input word. ### Claim 12 (depends on 11) The system of claim 11, wherein said specified bits are determined based on a value contained in said instruction register. ### Claim 13 (depends on 11) The system of claim 11, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 14 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes: a shift functional unit having a first input and a second input connected to said instruction register and an output, said first input representing a first input word, a multiplexer having a first input connected to said register file, a second input and a control input connected to said instruction register, and an output, a shift/rotate functional unit having a first input connected to said register file representing a second input word, a control input connected to said output of said multiplexer and an output, a first AND gate having a first input connected to said output of said shift functional unit, a second input connected to said output of said shift/rotate functional unit, and an output, a second AND gate having a first input connected to said register file, a second input connected to said output of said shift functional unit, and an output, and an OR gate having a first input connected to said output of said first AND gate, a second input connected to said output of said second AND gate, and an output, said output representing the result of "a load bit-field" operation that replaces specified bits of said second input word with corresponding bits of said first input word, wherein all other bits of said output are copied from said second input word. ### Claim 15 (depends on 14) The system of claim 14, wherein said specified bits of said second input word are determined based on a number contained in said instruction register. ### Claim 16 (depends on 14) The system of claim 14, wherein said specified bits of said second input word are determined based on a number contained in said register file. ### Claim 17 (depends on 14) The system of claim 14, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 18 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes: a multiplexer having a first input connected to said register file, a second input connected to said instruction register, a control input connected to said instruction register, and an output, and a shift/rotate functional unit having a first input connected to said register file, a second input connected to said output of said multiplexer, and an output, said output representing a result of a shift and rotate operation that shifts or rotates said first input of said shift/rotate functional unit a specified number of bit positions toward the most significant bit of said first input. ### Claim 19 (depends on 18) The system of claim 18, where said specified number is contained in said instruction register. ### Claim 20 (depends on 18) The system of claim 18, wherein said specified number is contained in said register file. ### Claim 21 (depends on 18) The system of claim 18, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 22 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as a queue for instructions before executing; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes: a shift functional unit having a first input and a second input connected to said instruction register and an output, a multiplexer having a first input connected to said register file, a second input and a control input connected to said instruction register, and an output, a shift/rotate functional unit having a first input connected to said register file representing an input word, a control input connected to said output of said multiplexer and an output, and an AND gate having a first input connected to said output of said shift functional unit, a second input connected to said output of said shift/rotate functional unit, and an output, said output representing the result of "an extract bit-field" operation that moves specified bits of said input word within said input word and resets all other bits of said input word to zero. ### Claim 23 (depends on 22) The system of claim 22, wherein said specified bits are determined based on a number contained in said instruction register. ### Claim 24 (depends on 22) The system of claim 22, wherein said specified bits are determined based on a number contained in said register file. ### Claim 25 (depends on 22) The system of claim 22, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed parallel. ### Claim 26 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes: a shift functional unit having a first input and a second input connected to said instruction register and an output, a first multiplexer having a first input connected to said register file, a second input and a control input connected to said instruction register, and an output, a shift/rotate functional unit having a first input connected to said register file representing an input word, a control input connected to said output of said first multiplexer and an output, a first AND gate having a first input connected to said output of said shift functional unit, a second input connected to said output of said shift/rotate functional unit, and an output, a second multiplexer having a first input connected to said output of said first AND gate, a second input and third input connected to said instruction register, and an output, a second AND gate having a first input connected to said register file, a second input connected to said output of said shift functional unit, and an output, an XOR gate having a first input connected to said output of said second multiplexer, a second input connected to said output of said second AND gate, and an output, and an OR gate having an input connected to said output of said XOR gate and an output, said output representing the result of "a compare bit-field" operation that sets a match flag register. ### Claim 27 (depends on 26) The system of claim 26, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 28 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing a clear bit-field operation that resets specified bits of an input word to zero and leaves all other bits of said input word intact. ### Claim 29 (depends on 28) The system of claim 28, wherein said specified bits are determined based on a value contained in said instruction register. ### Claim 30 (depends on 28) The system of claim 28, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 31 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing an isolate bit-field operation. ### Claim 32 (depends on 31) The system of claim 31, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 33 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing an extract bit-field operation that moves specified bits of an input word within said input word and resets all other bits of said input word to zero. ### Claim 34 (depends on 33) The system of claim 33, wherein said specified bits are determined based on a number contained in said instruction register. ### Claim 35 (depends on 33) The system of claim 33, wherein said specified bits are determined based on a number contained in said register file. ### Claim 36 (depends on 33) The system of claim 33, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 37 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing a load bit-field operation. ### Claim 38 (depends on 37) The system of claim 37, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 39 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing a compare bit-field operation. ### Claim 40 (depends on 39) The system of claim 39, wherein arithmetic operations performed by said arithmetic logic unit and logical operations performed by said bit processing unit are executed in parallel. ### Claim 41 A microprocessor for executing instructions within an instruction stream, comprising: an instruction register that functions as a queue for instructions before execution; a register file having a plurality of general purpose registers; an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations; and a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing a load literal field operation that stores a value stored in a literal field of an instruction to a target field within a word, wherein bits outside said target field are cleared to zero.