# US 5,704,022 A · Printer with high bandwidth compression architecture

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- Number: US 5,704,022 A
- Document ID: US5704022A
- Status: Granted
- Kind: A
- Application number: 08/641,872
- Filed: 1996-05-02
- Granted: 1997-12-30
- Earliest claimed: 1996-05-02
- Assignees: Lexmark International, Inc.
- Inventors: Bryan Leslie Ethington; John Francis Gostomski; Jeffrey Alan Minnick; Christopher Mark Songer
- Web page: https://patentgrep.com/patent/US5704022A

## CPC

- G06K 15/00: Arrangements for producing a permanent visual presentation of the output data {, e.g. computer output printers}(printing or plotting combined with another operation, e.g. with conveying, G06K17/00)
- G06K 2215/0062: combining generic and host data, e.g. filling a raster
- G06K 2215/0094: Colour printing
- G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS

## Abstract

To process bit maps for full color and other data-intense bit maps for printing, a data processing routine (FIG. 4) determines if a block at data within a page is not in color or is otherwise in a single value. Such data is stored in DRAM (28) in one bit per pel form. Other blocks are stored with eight bit for each pel. A table is then developed defining the contiguous order in a page (FIG. 6). An ASIC (32) then transfers the pel information in order of printing to a video RAM (40) with the eight bits restored for data stored in one bit per pel form. The data applied to that ASIC is decompressed.

## Claims

### Claim 1

A control system for a printer which requires at least 8 bit level information for each pel comprising a renderer to determine pel information including said level information from printer control information in blocks of predetermined size, each block describing part of a page, data processing means to determine if said level information is at one level for each block, data processing means responsive to said determination of one level to store in a first memory said blocks of one level in one bit for each pel form, means to store level data for each said block stored in one bit for each pel, a second memory to receive bit data and deliver that bit data to said printer for printing, means to store data for printing in said second memory corresponding to data in said first memory with said level information restored for each bit as said at least 8 bits for each pel, said level information being obtained from said level data stored for each block when the corresponding block was stored in one bit for each pel form.

### Claim 2 (depends on 1)

The control system as is claim 1 in which said second memory is a VRAM.

### Claim 3 (depends on 2)

The control system as in claim 2 also comprising means to compress said blocks stored in said first memory and means to decompress stored block information prior to said storing of data in said VRAM.

### Claim 4 (depends on 1)

The control system as in claim 1 also comprising means to compress said blocks stored in said first memory and means to decompress stored block information prior to said storing of data in said second memory.

### Claim 5

A control system for a printer comprising a renderer to determine pel information from printer control information in blocks, each block describing part of a page, a first memory to store all of said blocks defining a page, data processing means to define the location of said blocks in said first memory in order of the position of the information in said blocks with respect to the page which said blocks define, a second memory having an input for random access and a terminal for serial output to transfer data for printing, and a special purpose integrated circuit responsive to said defined location of said blocks to transfer data for printing to said input of said second memory in order for printing.

### Claim 6 (depends on 5)

The control system as in claim 5 in which said second memory is a VRAM.

### Claim 7 (depends on 5)

The control system as in claim 5 in which said printer requires at least 8 bit level information for each pel and said renderer determines pel information including said level information, and said control system also comprises data processing means to determine if said level information is at one level for each block, data processing means responsive to said determination of one level to store in said first memory said blocks of one level in one bit for each pel form, and means to store the level information for each said block stored in one bit for each pel form, and in which said special purpose integrated circuit transfers said blocks for printing with said level information restored for each bit as said at least 8 bits for each pel, said level information restored being obtained from said level information stored for each block when the corresponding block was in one bit for each pel form.

### Claim 8 (depends on 6)

The control system as in claim 6 in which said printer requires at least 8 bit level information for each pel and said renderer determines pel information including said level information, and said control system also comprises data processing means to determine if said level information is at one level for each block, data processing means responsive to said determination of one level to store in said first memory said blocks of one level in one bit for each pel form, and means to store the level information for each said block stored in one bit for each pel form, and in which said special purpose integrated circuit transfers said blocks for printing with said level information restored for each bit as said at least 8 bits for each pel, said level information restored being obtained from said level information stored for each block when the corresponding block was in one bit for each pel form.

### Claim 9 (depends on 8)

The control system as in claim 8 also comprising means to compress said blocks stored in said first memory and means to decompress stored block information prior to said storing of data in said VRAM.

### Claim 10 (depends on 5)

The control system as in claim 5 also comprising means to compress said blocks stored in said first memory and means to decompress stored block information prior to said storing of data in said second memory.

### Claim 11 (depends on 6)

The control system as in claim 6 also comprising means to compress said blocks stored in said first memory and means to decompress stored block information prior to said storing of data in said VRAM.

### Claim 12 (depends on 7)

The control system as in claim 7 also comprising means to compress said blocks stored in said first memory and means to decompress stored block information prior to said storing of data in said second memory.
