# US 5,703,956 A · External memory control circuit for sound field processing digital signal processor

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- Number: US 5,703,956 A
- Document ID: US5703956A
- Status: Granted
- Kind: A
- Application number: 08/522,707
- Filed: 1995-09-01
- Granted: 1997-12-30
- Earliest claimed: 1994-09-03
- Assignees: LG Electronics Inc.
- Inventors: Jong Hyun Kim
- Web page: https://patentgrep.com/patent/US5703956A

## CPC

- H04S 1/002: {Non-adaptive circuits, e.g. manually adjustable or static, for enhancing the sound image or the spatial distribution (control circuits for electronic adaptation of the sound field H04S7/30)}
- H04S: STEREOPHONIC SYSTEMS

## Abstract

An external memory control circuit for a sound field processing digital signal processor capable of obtaining continuous sound listening by shortening the time that sound is cut off upon a change of the sound field algorithm depending on the listening place (i.e., concert hall, meeting hall, church or the like). The external memory control circuit is constructed to utilize a mute function only for the time required to transfer the algorithm itself where a sound field processing circuit is realized using a DSP, thereby reducing the time that sound is cut off and thereby obtaining continuous sound listening even when the sound field algorithm is changed while listening.

## Claims

### Claim 1

An external memory control circuit for a digital signal processor adapted to execute an algorithm used in sound field processing for an input signal, the algorithm processing a first control signal and a second control signal, and to control a memory unit for obtaining a signal delay required in a computational operation for the sound field processing, comprising:
memory buffer control means for receiving the first control signal and the second control signal upon executing the algorithm, for controlling reading of data recorded in the memory unit in accordance with the first control signal and controlling recording of data externally input to the memory unit in accordance with the second control signal;
memory buffer means for buffering recorded data output from the memory unit and data to be externally input to the memory unit under the control of the memory buffer control means;
switching means for receiving a third control signal when a power is first supplied to the digital signal processor or when a change of the algorithm is made, and for outputting a selection control signal in accordance with the third control signal;
multiplexing means for selecting one of a data value output from the memory buffer means and a muting data value in accordance with the selection control signal from the switching means and outputting the thusly selected data value; and
direction selecting means for outputting the data value output from the multiplexing means to an internal data bus and for outputting data from an internal data bus to the memory buffer means under control of the memory buffer control means.

### Claim 2 (depends on 1)

The external memory control circuit in accordance with claim 1, wherein the switching means comprises:
a counter adapted to set an initial count value in response to the third control signal received to the switching means, to perform a counting operation after setting the initial count value and to stop the counting operation when the counted value corresponds to a predetermined value; and
a multiplexer control unit for outputting the selection control signal to the multiplexing means based on the counted value.

### Claim 3 (depends on 2)

The external memory control circuit in accordance with claim 2, wherein the counter has a parallel loading function for loading the initial count value in a parallel manner when the third control signal is received to the switching means.

### Claim 4 (depends on 2)

The external memory control circuit in accordance with claim 2, wherein the multiplexer control unit comprises:
an OR gate for ORing output signals from the counter and thereby outputting a selection control signal; and
an AND gate for ANDing the selection control signal from the OR gate and a sampling clock signal and sending the resulting signal to the counter as a clock signal.

### Claim 5 (depends on 2)

The external memory control circuit in accordance with claim 2, wherein the counter is a down counter.

### Claim 6 (depends on 2)

The external memory control circuit in accordance with claim 2, wherein the third control signal is received to the switching means when the first control signal is received to the memory buffer control means.

### Claim 7 (depends on 2)

The external memory control circuit in accordance with claim 2, wherein the switching means does not operate when the second control signal is received to the memory buffer means.

### Claim 8 (depends on 1)

The external memory control circuit in accordance with claim 1, wherein the switching means comprises a flip-flop and wherein the algorithm checks a variable for setting or resetting the flip-flop at every sampling interval so that the flip-flop outputs a selection control signal by executing a deduction operation when the variable is not less than a predetermined value, thereby setting the flip-flop while resetting the flip-flop when the variable is less than the predetermined value.