# US 5,703,886 A · Error detecting apparatus for packet exchange

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- Number: US 5,703,886 A
- Document ID: US5703886A
- Status: Granted
- Kind: A
- Application number: 08/616,301
- Filed: 1996-03-15
- Granted: 1997-12-30
- Earliest claimed: 1995-03-16
- Assignees: Hyundai Electronics Industries Co., Ltd.
- Inventors: Seong Sam Lee; Yong Don Kwon
- Web page: https://patentgrep.com/patent/US5703886A

## CPC

- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

An error detecting apparatus for a packet exchange in which a block coding technique capable of using a data width of 16 bits while using a bus width of 24 bits is applied to drive the common bus of the packet exchange, thereby not only obtaining a bit exchange speed being double that of a triplicated common bus, but also detecting errors and correcting the detected errors. The apparatus includes a pair of encoding units each adapted to encode data of 8 bits and four code bits for an error detection, thereby generating a coded vector of 12 bits, a common bus adapted to interface the 12-bit coded vectors respectively generated from the encoding units, and a pair of decoding units adapted to share the common bus with each other, thereby respectively receiving the coded 12-bit vectors, each decoding unit extracting original 8-bit data from the received 12-bit vector, thereby detecting and correcting errors.

## Claims

### Claim 1

An error detecting apparatus for a packet exchange comprising:
a pair of encoding means each adapted to encode 8-bit data and four code bits for an error detection, thereby generating a 12-bit coded vector;
a common bus adapted to interface the 12-bit coded vectors respectively generated from the encoding means; and
a pair of decoding means adapted to share the common bus with each other, thereby respectively receiving the coded 12-bit vectors, each decoding means extracting original 8-bit data from the received 12-bit vector, thereby detecting and correcting errors.

### Claim 2 (depends on 1)

The error detecting apparatus in accordance with claim 1, wherein a first one of decoding means comprises:
a first decoder for exclusively logically operating the 12-bit vector received through the common bus, thereby generating four code bits;
a second decoder for logically multiplying the four code bits generated from the first decoder, thereby generating eight code bits; and
a third decoder for exclusively logically operating the eight code bits generated from the second decoder and the 8-bit vector received through the common bus, thereby extracting original 8-bit data.

### Claim 3 (depends on 2)

The error detecting apparatus in accordance with claim 2, wherein the first decoder carries out a decoding operation for generating the four code bits in the following manner:
s0=y3.sub.61 y4.sub.61 y5.sub.61 y6.sub.61 y7.sub.61 y8, s1=y1.sub.61 y2.sub.61 y5.sub.61 y6.sub.61 y7.sub.61 y8,
s2=y0.sub.61 y2.sub.61 y4.sub.61 y7.sub.61 y10, s3=y0.sub.61 y1.sub.61 y3.sub.61 y6.sub.61 y11
where, yi represents the 8-bit vector received through the common bus, and s0 to s3 represent four code bits respectively output from the first decoder.

### Claim 4 (depends on 2)

The error detecting apparatus in accordance with claim 2, wherein the second decoder carries out a decoding operation for generating the eight code bits in the following manner:
E.sub.0 =S.sub.0 .multidot.S.sub.1 .multidot.S.sub.2 .multidot.S.sub.3, E.sub.1 =S.sub.0 .multidot.S.sub.1 .multidot.S.sub.2 .multidot.S.sub.3,
E.sub.2 =S.sub.0 .multidot.S.sub.1 .multidot.S.sub.2 .multidot.S.sub.3 , E.sub.3 =S.sub.0 .multidot.S.sub.1 .multidot.S.sub.2 .multidot.S.sub.3,
E.sub.4 =S.sub.0 .multidot.S.sub.1 .multidot.S.sub.2 .multidot.S.sub.3 , E.sub.5 =S.sub.0 .multidot.S.sub.1 .multidot.S.sub.2 .multidot.S.sub.3 ,
E.sub.6 =S.sub.0 .multidot.S.sub.1 .multidot.S.sub.2 .multidot.S.sub.3, E.sub.7 =S.sub.0 .multidot.S.sub.1 .multidot.S.sub.2 .multidot.S.sub.3 ,
where, s0 to s3 represent input code bits, respectively, and E0 to E7 represent eight code bits respectively output from the second decoder.