# US 5,703,884 A · Scanning pass test circuit

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- Number: US 5,703,884 A
- Document ID: US5703884A
- Status: Granted
- Kind: A
- Application number: 08/665,538
- Filed: 1996-06-18
- Granted: 1997-12-30
- Earliest claimed: 1995-06-23
- Assignees: NEC Corporation
- Inventors: Hideharu Ozaki
- Web page: https://patentgrep.com/patent/US5703884A

## CPC

- G01R 31/318558: {Addressing or selecting of subparts of the device under test}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A shift register constituting a scanning pass test circuit is divided into a plurality of groups, and bypass selectors are inserted into the divided positions of the shift register. A latch circuit is connected to each of the clock signal terminals of the flip-flop circuits which are disposed at the first stage of the flip-flop circuit groups.

## Claims

### Claim 1

A scanning pass test circuit comprising:
a scan-in terminal;
a scan-out terminal;
a plurality of flip-flops connected together in series, wherein said plurality of flip-flops are divided into groups to form a first shift register and a second shift register;
first means for selectively connecting said scan-in terminal with an input node of either of said first and second shift registers for shifting input data inputted to said scan-in terminal;
second means for selectively connecting said scan-out terminal with an output node of said first shift register when said first means connects said scan-in terminal with an input of said first shift register, and for selectively connecting said scan-out terminal with an output node of said second shift register when said first means connects said scan-in terminal with an input of said second shift register; and
third means for supplying a shift clock to said first shift register and not supplying said shift clock to said second shift register when said first means connects said scan-in terminal with said input of said first shift register.

### Claim 2 (depends on 1)

The scanning pass test circuit as claimed in claim 1 further comprising fourth means for setting a content of either of said first and second shift registers to an output value from a combination circuit before either of said first and second shift registers shift said content out to said scan-out terminal.

### Claim 3 (depends on 1)

The scanning pass test circuit as claimed in claim 1, wherein said third means comprises latch circuits for receiving said shift clock and one of a plurality of bypass control signals,
wherein said latch circuits output said shift clock or hold said shift clock according to a logic level of said one of said bypass control signals.

### Claim 4

A scanning pass test circuit for testing a combination circuit comprising:
a shift register connected to an output selector, wherein said output selector includes a first input connected with an output of said shift register and a second input connected with an input of said shift register; and
shift clock supply means, attached to said shift register for supplying a series of shift clocks thereto,
wherein said shift clock supply means supplies said shift clock to said and when said output selector selects said first input and does not supply said shift clock to said shift register when said output selector selects said second input.

### Claim 5 (depends on 4)

The scanning pass test circuit as claimed in claim 4, wherein said shift clock supply means comprises a latch circuit receiving said shift clock and a control signals.