# US 5,703,829 A · Synchronous type semiconductor memory device which can be adapted to high frequency system clock signal

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- Number: US 5,703,829 A
- Document ID: US5703829A
- Status: Granted
- Kind: A
- Application number: 08/681,428
- Filed: 1996-07-23
- Granted: 1997-12-30
- Earliest claimed: 1995-12-28
- Assignees: Mitsubishi Denki Kabushiki Kaisha
- Inventors: Tomio Suzuki; Shigeru Mori; Takayuki Miyamoto
- Web page: https://patentgrep.com/patent/US5703829A

## CPC

- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In a pipeline burst EDO operation, a latency circuit 215 detects change of an internal column address strobe signal ZCASF from an active state to a non-active sate in the first cycle, and brings a signal OEMB into an active state. When a writing operation mode is specified, and an internal output enable signal ZOEF is in an active state, an output buffer control signal OEM attains an active state in response to the first activation edge of the internal column address strobe signal ZCASF after activation of the signal OEMB. Since the signal OEMB has already been in an active state in the first cycle of the signal ZCASF, a delay time for change of the signal OEM in response to activation of the signal ZCASF in the second cycle can be decreased.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a memory cell array having a plurality of memory cells arranged in rows and columns;
column selecting means activated at the time of activation of a column address strobe signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal;
a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns;
data output means for sequentially providing data amplified by said plurality of data reading and amplifying means to an output buffer in synchronism with activation of said column address strobe signal; and
output buffer control means responsive to any transition of said column address strobe signal from an active state to a non-active state for activating said output buffer.

### Claim 2

A semiconductor memory device sequentially providing a plurality of read data from a plurality of memory cells selected simultaneously, in synchronism with a change cycle of a column address strobe signal in a predetermined operation mode, comprising:
a memory cell array having a plurality of memory cells arranged in rows and columns;
column selecting means responsive to a first activation transition of said column address strobe signal for simultaneously selecting a plurality of columns of said memory cell array specified by an external address signal;
a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns;
latch means for receiving and holding outputs of said plurality of data reading and amplifying means;
data output means receiving outputs of said latch means and responsive to an activation transition of said column address strobe signal for sequentially outputting said outputs of said latch means;
output driving means receiving outputs of said data output means and responsive to an output buffer activation signal for externally outputting corresponding signals; and
output buffer control means responsive to a first deactivation transition of said column address strobe signal for outputting said output buffer activation signal.

### Claim 3 (depends on 2)

The semiconductor memory device according to claim 2, wherein
said first activation transition and said first deactivation transition are included in the same cycle of change of said column address strobe signal.

### Claim 4 (depends on 2)

The semiconductor memory device according to claim 2, wherein
said output buffer control means includes
means responsive to said first deactivation transition of said column address strobe signal for outputting an active internal output control signal, and
means for sensing activation of said column address strobe signal for maintaining said output buffer control signal in an active state in a period during which an external read operation control signal and said internal output control signal are both active.

### Claim 5

A semiconductor memory device, comprising:
a memory cell array having a plurality of memory cells arranged in rows and columns;
synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of a column address strobe signal;
column selecting means activated at the time of activation of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal; and
data input/output means for sequentially transmitting and receiving data between memory cells of a corresponding column among said plurality of columns and the outside world in synchronism with activation of said internal clock signal.

### Claim 6

A semiconductor memory device, comprising:
a memory cell array having a plurality of memory cells arranged in rows and columns;
synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of a column address strobe signal;
column selecting means activated at the time of activation of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal;
a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; and
output control means for sequentially outputting data amplified by said plurality of data reading and amplifying means, in synchronism with activation of said internal clock signal.

### Claim 7

A semiconductor memory device for sequentially outputting a plurality of read data from a plurality of memory cells selected simultaneously, in synchronism with an activation cycle of a column address strobe signal in a predetermined operation mode, comprising:
a memory cell array having a plurality of memory cells arranged in rows and columns;
synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of said column address strobe signal;
column selecting means responsive to a first activation transition of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array specified by an external address signal;
a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns;
latch means for receiving and holding outputs of said plurality of data reading and amplifying means; and
output control means receiving outputs of said latch means and responsive to an activation transition after said first activation transition of said internal clock signal for sequentially and externally providing said outputs of said latch means.

### Claim 8 (depends on 7)

The semiconductor memory device according to claim 7, wherein
said synchronization signal generating means includes
a logic circuit having first and second input nodes and responsive to activation of an input signal to any one of the input nodes for inverting a level of an output signal, and
a delay circuit receiving said column address strobe signal for outputting the same to said first input node with a delay time corresponding to said predetermined pulse length,
said column address strobe signal being applied to said second input node.

### Claim 9

A semiconductor memory device, comprising:
a memory cell array having a plurality of memory cells arranged in rows and columns;
synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of a column address strobe signal;
column selecting means activated at the time of activation of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal;
a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns;
data output means for sequentially applying data amplified by said plurality of data reading and amplifying means to an output buffer, in synchronism with activation of said internal clock signal; and
output buffer control means responsive to any transition of said internal clock signal from an active state to a non-active state for activating said output buffer.

### Claim 10

A semiconductor memory device for sequentially outputting a plurality of read data from a plurality of memory cells selected simultaneously, in synchronism with an activation cycle of a column address strobe signal in a predetermined operation mode, comprising:
a memory cell array having a plurality of memory cells arranged in rows and columns;
synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of said column address strobe signal;
column selecting means responsive to a first activation transition of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array specified by an external address signal;
a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns;
latch means for receiving and holding outputs of said plurality of data reading and amplifying means; and
data output means receiving outputs of said latch means and responsive to an activation transition of said internal clock signal for sequentially providing said outputs of said latch means;
output driving means receiving an output of said data output means and responsive to an output buffer activation signal for externally outputting a corresponding signal; and output buffer control means responsive to a first deactivation transition of said internal clock signal for outputting said output buffer activation signal.

### Claim 11 (depends on 10)

The semiconductor memory device according to claim 10, wherein
said first activation transition and said first deactivation transition are included in the same cycle of change of said column address strobe signal.