# US 5,703,828 A · Semiconductor memory

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- Number: US 5,703,828 A
- Document ID: US5703828A
- Status: Granted
- Kind: A
- Application number: 08/580,622
- Filed: 1995-12-29
- Granted: 1997-12-30
- Earliest claimed: 1992-10-02
- Inventors: Churoo Park; Hyun-Soon Jang; Chull-Soo Kim; Myung-Ho Kim; Seung-Hun Lee; Si-Yeol Lee; Ho-Cheol Lee; Tae-Jin Kim; Yun-Ho Choi
- Web page: https://patentgrep.com/patent/US5703828A

## CPC

- G11C 7/1018: {Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters}
- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 7/225: {Clock input buffers}
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/408: Address circuits
- G11C 11/4082: {Address Buffers; level conversion circuits}
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 2207/2281: Timing of a read operation
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

## Claims

### Claim 1

A dynamic random access memory comprising:
a plurality of memory banks, each bank including a plurality of memory cells having addresses associated therewith and a separate address buffer for qenerating addresses and operable in one of an active cycle and a precharge cycle at any one time;
first means for receiving a row address strobe signal and producing a first signal;
second means for receiving a column address strobe signal and producing a second signal;
third means for receiving a write enable signal and producing a third signal;
address input means for receiving a portion of one of said addresses to indicate selection of one of said memory banks; and
logic means, responsive to said first, second and third signals and said one address portion, for generating a separate row address strobe clock for each of said plurality of memory banks and allow for each memory bank to operate with overlapping active cycles using addresses from said separate address buffer associated with each said memory bank.

### Claim 2 (depends on 1)

A semiconductor memory circuit according to claim 1 wherein said first and third signals are produced in synchronism with an external clock.

### Claim 3 (depends on 1)

A semiconductor memory circuit according to claim 1 wherein said logic means detects a normal read operation mode and precharging of said plurality of memory banks takes place simultaneously.

### Claim 4 (depends on 3)

A semiconductor memory circuit according to claim 3 wherein said first and third signals are produced in synchronism with an external clock.

### Claim 5 (depends on 1)

A semiconductor memory circuit according to claim 1 wherein said logic means detects an interleave read operation mode and precharging of one of said memory banks takes place during a portion of a first active cycle that does not overlap with precharging of another of said memory banks during a first precharge cycle that overlaps with said first active cycle.

### Claim 6 (depends on 5)

A semiconductor memory circuit according to claim 5 wherein said first and third signals are produced in synchronism with an external clock.

### Claim 7 (depends on 1)

A semiconductor memory circuit according to claim 1 wherein each of said separate address buffers generate a different address for each of said banks when each of said banks are simultaneously in an active cycle.

### Claim 8

A dynamic random access memory comprising:
a plurality of memory banks, each bank including a plurality of memory cells having addresses associated therewith and a separate address buffer for generating addresses and operable in one of an active cycle and a precharge cycle at any one time;
row address strobe input circuitry which receives a row address strobe signal and produces a first signal;
column address strobe input circuitry which receives a column address strobe signal and produces a second signal;
write enable input circuitry which receives a write enable signal and produces a third signal;
an address input for receiving a portion of one of said addresses to indicate selection of one of said memory banks; and
a logic circuit, responsive to said first, second and third signals and said one address portion, for generating a separate row address strobe clock for each of said plurality of memory banks and allow for each memory bank to operate with overlapping active cycles using addresses from said separate address buffer associated with each said memory bank.

### Claim 9 (depends on 8)

A semiconductor memory circuit according to claim 8 wherein said first and third signals are produced in synchronism with an external clock.

### Claim 10 (depends on 8)

A semiconductor memory circuit according to claim 8 wherein said logic circuit detects a normal read operation mode and precharging of said plurality of memory banks takes place simultaneously.

### Claim 11 (depends on 10)

A semiconductor memory circuit according to claim 10 wherein said first and third signals are produced in synchronism with an external clock.

### Claim 12 (depends on 8)

A semiconductor memory circuit according to claim 8 wherein said logic circuit detects an interleave read operation mode and precharging of one of said memory banks takes place during a portion of a first active cycle that does not overlap with precharging of another of said memory banks during a first precharge cycle that overlaps with said first active cycle.

### Claim 13 (depends on 12)

A semiconductor memory circuit according to claim 12 wherein said first and third signals are produced in synchronism with an external clock.

### Claim 14 (depends on 8)

A semiconductor memory circuit according to claim 8 wherein each of said separate address buffers generate a different address for each of said banks when each of said banks are simultaneously in an active cycle.