# US 5,703,827 A · Method and structure for generating a boosted word line voltage and a back bias voltage for a memory array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,703,827 A - Document ID: US5703827A - Status: Granted - Kind: A - Application number: 08/610,108 - Filed: 1996-02-29 - Granted: 1997-12-30 - Earliest claimed: 1996-02-29 - Assignees: Monolithic System Technology, Inc. - Inventors: Wingyu Leung; Jeffrey J. Lin - Web page: https://patentgrep.com/patent/US5703827A ## CPC - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 5/146: {Substrate bias generators (G11C5/141 takes precedence)} - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method and structure for generating a boosted word line voltage for a memory array, such as a DRAM array. To ensure that an adequate voltage is applied to the word line of the memory array during write operations, the word line driver circuit is connected to a boost voltage generator which provides a substantially constant, regulated voltage which is boosted to a level which is approximately equal to the V.sub.CC supply voltage plus the threshold voltage of the memory cell pass transistor. A bias voltage generator provides a negative voltage which is used to bias the substrate of the memory array. The boosted voltage generator and the bias voltage generator can be operated in response to the same clock signal used to operate the memory array. A latch-up prevention circuit is provided to ensure that the word line driver circuit does not latch-up during power-on before an adequate boost voltage has been established. ## Claims ### Claim 1 A semiconductor memory fabricated on a substrate, the memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the memory comprising: a first voltage generation circuit coupled to the first and second voltage supplies, the voltage generation circuit generating a substantially constant boosted voltage which exceeds the first supply voltage; a driver circuit coupled to the first voltage generation circuit and the word line, the driver circuit being adapted to selectively apply the boosted voltage to the word line; and a second voltage generation circuit coupled to the first and second voltage supplies, the second voltage generation circuit generating a substantially constant bias voltage generation which is less than the second supply voltage, the second voltage generation circuit being coupled to the substrate, thereby applying the bias voltage to the substrate. ### Claim 2 (depends on 1) The memory of claim 1, wherein the memory further comprises a memory cell coupled to the word line, the memory cell comprising a transistor having a threshold voltage, wherein the boosted voltage exceeds the first supply voltage by the threshold voltage of the transistor. ### Claim 3 (depends on 2) The memory of claim 2, wherein the memory cell is a dynamic random access memory (DRAM) cell. ### Claim 4 (depends on 1) The memory of claim 1, wherein the first voltage generation circuit comprises: a charge pump circuit which generates an output voltage in response to a master clock signal; and a regulator circuit coupled to the charge pump circuit, wherein the regulator circuit enables the charge pump circuit when the output voltage is less than the boosted voltage and wherein the regulator circuit disables the charge pump circuit when the output voltage is greater than the boosted voltage. ### Claim 5 (depends on 4) The memory of claim 4, wherein the charge pump comprises a pair of capacitors which are alternately charged and discharged in response to the master clock signal to generate the output voltage. ### Claim 6 A semiconductor memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the memory comprising: a voltage generation circuit coupled to the first and second voltage supplies, the voltage generation circuit generating a substantially constant boosted voltage which exceeds the first supply voltage; a driver circuit coupled to the voltage generation circuit and the word line, the driver circuit being adapted to selectively apply the boosted voltage to the word line; a charge pump circuit which generates an output voltage in response to a master clock signal; a regulator circuit coupled to the charge pump circuit, wherein the regulator circuit enables the charge pump circuit when the output voltage is less than the boosted voltage and wherein the regulator circuit disables the charge pump circuit when the output voltage is greater than the boosted voltage; and a clock synchronization circuit for receiving an external clock signal, and in response, generating the master clock signal, the master clock signal being synchronized with the external clock signal. ### Claim 7 (depends on 6) The memory of claim 6, wherein the memory is operated in response to the master clock signal. ### Claim 8 (depends on 6) The memory of claim 6, wherein the clock synchronization circuit and the voltage generation circuit are located on the same chip. ### Claim 9 A semiconductor memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the memory comprising: a voltage generation circuit coupled to the first and second voltage supplies, the voltage generation circuit generating a substantially constant boosted voltage which exceeds the first supply voltage, wherein the voltage generation circuit comprises a latch-up prevention circuit which couples the driver circuit to the first voltage supply during power-on of the memory, and couples the driver circuit to receive the boosted voltage during normal operation of the memory; and a driver circuit coupled to the voltage generation circuit and the word line, the driver circuit being adapted to selectively apply the boosted voltage to the word line. ### Claim 10 A semiconductor memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the memory comprising: a voltage generation circuit coupled to the first and second voltage supplies, the voltage generation circuit generating a substantially constant boosted voltage which exceeds the first supply voltage; a driver circuit coupled to the voltage generation circuit and the word line, the driver circuit being adapted to selectively apply the boosted voltage to the word line; a second voltage generation circuit coupled to the first and second voltage supplies, the second voltage generation circuit generating a substantially constant bias voltage which is less than the second supply voltage, wherein the second voltage generation circuit comprises: a charge pump circuit for generating an output voltage in response to a clock signal; a regulator circuit coupled to the charge pump circuit, wherein the regulator circuit enables the charge pump circuit when the output voltage is greater than the bias voltage and wherein the regulator circuit disables the charge pump circuit when the output voltage is less than the bias voltage; a ring oscillator circuit for generating a start-up clock signal; and a clock selector circuit which provides the start-up clock signal to the charge pump circuit during power-on of the memory, and provides the master clock signal to the charge pump circuit during normal operation of the memory. ### Claim 11 (depends on 10) The memory of claim 10, further comprising, means for enabling the ring oscillator circuit during power-on of the memory and for disabling the ring oscillator circuit during normal operation of the memory. ### Claim 12 A semiconductor memory fabricated on a substrate, the memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the memory comprising: a first voltage generation circuit coupled to the first and second voltage supplies, the voltage generation circuit generating a substantially constant boosted voltage which is less than the second supply voltage; and a driver circuit coupled to the first voltage generation circuit and the word line, the driver circuit being adapted to selectively apply the boosted voltage to the word line; and a second voltage generation circuit coupled to the first and second voltage supplies, the second voltage generation circuit generating a substantially constant bias voltage which is greater than the first supply voltage, the second voltage generation circuit being coupled to the substrate, thereby applying the bias voltage to the substrate. ### Claim 13 A method of operating a semiconductor memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the method comprising the steps of: generating a substantially constant boosted voltage which exceeds the first supply voltage; applying the boosted voltage to a driver circuit which is coupled to the word line, wherein the step of generating the boosted voltage comprises the steps of: applying a master clock signal to a voltage generation circuit, wherein the voltage generation circuit generates the boosted voltage in response to the master clock signal; and regulating the boosted voltage by controlling the application of the master clock signal to the voltage generation circuit; receiving an external clock signal; and generating the master clock signal in response to the external clock signal, the master clock signal being synchronized with the external clock signal. ### Claim 14 (depends on 13) The method of claim 13, further comprising the step of operating the memory circuit in response to the master clock signal. ### Claim 15 A method of operating a semiconductor memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the method comprising the steps of: generating a substantially constant boosted voltage which exceeds the first supply voltage; applying the boosted voltage to a driver circuit which is coupled to the word line, wherein the step of generating the boosted voltage comprises the steps of: applying a master clock signal to a voltage generation circuit, wherein the voltage generation circuit generates the boosted voltage in response to the master clock signal; and regulating the boosted voltage by controlling the application of the master clock signal to the voltage generation circuit; and generating a substantially constant bias voltage which is less than the second supply voltage in response to the master clock signal. ### Claim 16 (depends on 15) The method of claim 15, wherein the memory circuit is fabricated on a substrate, the method further comprising the step of applying the bias voltage to the substrate. ### Claim 17 (depends on 15) The method of claim 15, wherein the step of generating the bias voltage comprises the steps of: generating an output voltage by a voltage generation circuit in response to the master clock signal; and regulating the output voltage to approximate the bias voltage by controlling the application of the master clock signal to the voltage generation circuit. ### Claim 18 (depends on 15) The method of claim 15, further comprising the steps of: generating a start-up clock signal; and applying the start-up clock signal to the voltage generation circuit during power-on of the memory circuit; and applying the master clock signal to the voltage generation circuit during normal operating conditions of the memory circuit. ### Claim 19 A method of operating a semiconductor memory fabricated on a substrate, the memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the method comprising the steps of: generating a substantially constant boosted voltage which is less than the second supply voltage; applying the boosted voltage to a driver circuit which is coupled to the word line, wherein the step of generating the boosted voltage comprises the steps of: applying a master clock signal to a voltage generation circuit, wherein the voltage generation circuit generates the boosted voltage in response to the master clock signal; and regulating the boosted voltage by controlling the application of the master clock signal to the voltage generation circuit; and generating a substantially constant bias voltage which is greater than the first supply voltage in response to the master clock signal; and applying the bias voltage to the substrate. ### Claim 20 (depends on 15) The method of claim 15, wherein the step of generating the boosted voltage comprises the steps of: alternately charging a pair of capacitors in response to the master clock signal; and alternately discharging the pair of capacitors in response to the master clock signal.