# US 5,703,821 A · High performance single port RAM generator architecture

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- Number: US 5,703,821 A
- Document ID: US5703821A
- Status: Granted
- Kind: A
- Application number: 08/562,736
- Filed: 1995-11-27
- Granted: 1997-12-30
- Earliest claimed: 1992-11-30
- Assignees: SGS-Thomson Microelectronics S.A.
- Inventors: Andrea Baroni; Giovanni Mastrodomenico; Michele Taliercio; Piero Capocelli; Luigi Carro; Rajamohan Varambally
- Web page: https://patentgrep.com/patent/US5703821A

## CPC

- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

## Claims

### Claim 1

A memory device comprising:
a static RAM matrix; and
a self timed architecture, wherein the self timed architecture comprises a dummy row and a dummy column having, respectively, an equivalent load of a word line and of a bit column of said matrix, said dummy column being discharged at a faster rate than a corresponding bit column.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein said dummy row has an equivalent load of a word line and corresponds to a row of said memory matrix.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein said dummy column has an equivalent load of a bit line and corresponds to a column of said memory matrix.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein said dummy column comprises an input portion with an array of discharge cells.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein each discharge cell of the array of discharge cells includes at least two transistors, each of which is connected between a dummy column and ground.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein said at least two transistors are MOS type, with a first transistor having a drain connected to the dummy column and a source coupled to a drain of the second transistor, and a second transistor having a source connected to ground and a gate connected to the supply voltage.

### Claim 7 (depends on 5)

The memory device of claim 5, wherein all gate terminals of the first transistors are connected together and receive a same dummy row selection signal.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein said static RAM matrix comprises basic SRAM cells including a plurality of inverter latches connected back to back with corresponding pass transistors connected to the bit line.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the self timed architecture further include a control logic with a duty cycle independent read cycle activated by a falling edge of a clock signal, such control logic having an output connected to a dummy row.

### Claim 10 (depends on 1)

The memory device of claim 1, further comprising an output line of latches and buffers being enabled by a falling edge of at least one of a clock signal and an output enable signal.

### Claim 11

A single-port random-access memory comprising:
a decoder;
a read and write passgate;
a sense amplifier;
an output latch and buffer;
a static RAM matrix including at least one row connected to the decoder, and at least one column connected to the read and write passgate, the sense amplifier, and the output latch and buffer; and
a self-timed control-logic, connected to the decoder and further connected to the sense amplifier of the matrix by a driver block, including a dummy row and dummy column.

### Claim 12 (depends on 11)

The single port random-access memory of claim 11 wherein each row of the rows and each column of the column of the matrix comprise SRAM cells including a plurality of inverters connected to pass transistors which are connected to corresponding bit lines of the matrix.

### Claim 13 (depends on 12)

The single port random-access memory of claim 12 wherein the plurality of inverters comprise connections between a reference voltage and a supply voltage of a CMOS structure with a first N-channel MOS transistor connected to a second P-channel MOS transistor.

### Claim 14 (depends on 11)

The single port random-access memory of claim 11 wherein the dummy row provides equivalent loading of a word line to the self-timed control-logic and corresponds to a row of the matrix.

### Claim 15 (depends on 11)

The single port random-access memory of claim 11 wherein the dummy column provides equivalent loading of a bit line of the bit lines to the self-timed control-logic and corresponds to a column of the columns in the matrix.

### Claim 16 (depends on 15)

The single port random-access memory of claim 15 wherein the dummy column includes an array of discharge cells for a means of discharging the dummy column at a rate faster than the corresponding column of the matrix.

### Claim 17 (depends on 16)

The single port random-access memory of claim 16 wherein the discharge cells include a plurality of transistors, each of which is connected to the dummy column and the reference voltage.

### Claim 18 (depends on 17)

The single port random-access memory of claim 17 wherein the plurality of transistors are each of a MOS type, with a drain of a first transistor connected to the dummy column, a source of the first transistor connected to a drain of the second transistor, a source of a second transistor connected to the reference voltage and a gate of the second transistor connected to the supply voltage.

### Claim 19 (depends on 17)

The single port random-access memory of claim 17 wherein the gate of all of the first transistors are connected together for a means of receiving a same dummy row selection signal.

### Claim 20 (depends on 11)

The single port random-access memory of claim 11 wherein the self-timed control includes a duty cycle independent read cycle activated by a falling edge of a clock signal and an output connected to the dummy row.

### Claim 21 (depends on 11)

The single port random-access memory of claim 11 wherein the output latch and buffer includes an output line enabled by a falling edge of a clock signal and an output enable signal.

### Claim 22

A method for operating a random access memory, comprising the steps of:
selecting one of a plurality of memory cells within a memory matrix having rows and columns, the one of the plurality of memory cells providing an output;
selecting a dummy column that has a substantially equivalent load of a column of the matrix, to discharge the dummy column; and
latching the output of the one of the plurality of memory cells in response to the discharge of the dummy column.

### Claim 23 (depends on 22)

The method of claim 22, wherein the step of selecting the dummy cell includes controlling the dummy cell to discharge at a rate that is faster than a rate of a corresponding bit column of the memory matrix.

### Claim 24 (depends on 22)

The method of claim 22, wherein the step of selecting the dummy column includes activating an array of discharge cells.

### Claim 25 (depends on 22)

The method of claim 22, wherein the step of selecting the dummy column includes discharging a plurality of transistors, each of which is connected between the dummy column and a reference voltage.

### Claim 26 (depends on 25)

The method of claim 25, wherein each of the plurality of transistors is of a MOS type, with a first transistor of the plurality of transistors having a drain connected to the dummy column and a source coupled to the drain of a second transistor of the plurality of transistors, the second transistor having a source connected to ground and a gate connected to the reference voltage.

### Claim 27 (depends on 25)

The method of claim 25, wherein the gate of each first transistor receives a same dummy row selection signal.

### Claim 28 (depends on 22)

The method of claim 22, wherein the step of selecting the dummy column includes activating a duty cycle that is independent of a read cycle, in response to a falling edge of a clock signal.

### Claim 29 (depends on 22)

The method of claim 22, wherein the step of latching includes selecting an output amplifier and de-selecting the one of the plurality of memory cells.

### Claim 30 (depends on 22)

The method of claim 22, wherein the step of latching is performed in response to a discharge of the dummy column of substantially half of a supply voltage that supplies the dummy column.

### Claim 31

An apparatus for operating a random access memory, comprising:
means for selecting one of a plurality of memory cells within a memory matrix having rows and columns, the one of the plurality of memory cells providing an output;
means for selecting a dummy column that has a substantially equivalent load of a column of the matrix, to discharge the dummy column; and
means for latching the output of the one of the plurality of memory cells in response to the discharge of the dummy column.

### Claim 32 (depends on 31)

The apparatus of claim 31, wherein the means for selecting the dummy column includes means for controlling the dummy cell to discharge at a rate that is faster than a rate of a corresponding bit column of the memory matrix.

### Claim 33 (depends on 31)

The apparatus of claim 31, wherein the means for selecting the dummy column includes means for activating an array of discharge cells.

### Claim 34 (depends on 31)

The apparatus of claim 31, wherein the means for selecting the dummy column includes means for discharging a plurality of transistors, each of which is connected between the dummy column and a reference voltage.

### Claim 35 (depends on 34)

The apparatus of claim 34, whereto each of the plurality of transistors is of a MOS type, with a first transistor of the plurality of transistors having a drain connected to the dummy column and a source coupled to the drain of second transistor of the plurality of transistors, the second transistor having a source connected to ground and a gate connected to the reference voltage.

### Claim 36 (depends on 35)

The apparatus of claim 35, wherein the gate each first transistor receives a same dummy row selection signal.

### Claim 37 (depends on 31)

The apparatus of claim 31, wherein the means for selecting the dummy column includes means for activating a duty cycle that is independent of a read cycle, in response to a falling edge of a clock signal.

### Claim 38 (depends on 31)

The apparatus of claim 31, wherein the means for latching includes means for selecting an output amplifier and for de-selecting the one of the plurality of memory cells.

### Claim 39 (depends on 31)

The apparatus of claim 31, wherein the means for latching is responsive to a discharge of the dummy column of substantially half of a supply voltage that supplies the dummy column.