# US 5,703,812 A · Multi-bit data output buffer for semiconductor memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 5,703,812 A
- Document ID: US5703812A
- Status: Granted
- Kind: A
- Application number: 08/674,160
- Filed: 1996-07-01
- Granted: 1997-12-30
- Earliest claimed: 1995-06-30
- Assignees: Hyundai Electronics Industries Co., Ltd.
- Inventors: Myung Sun Ryu
- Web page: https://patentgrep.com/patent/US5703812A

## CPC

- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- H03K 19/00361: {in field effect transistor circuits}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A multi-bit data output buffer for a semiconductor memory device, comprising a data input circuit for inputting at least two bit data, at least two bit data buffering circuits, each of at least two bit data buffering circuits buffering a corresponding one of at least two bit data from the data input circuit, and a bit data comparison circuit for controlling the amounts of current flowing to at least two bit data buffering circuits according to logic values of at least two bit data from the data input circuit. According to the present invention, the multi-bit data output buffer is capable of minimizing the generation of noise in the output data and enhancing a response speed of the output data with respect to the input data.

## Claims

### Claim 1

A multi-bit data output buffer for a semiconductor memory device, the buffer comprising:
data input means for inputting at least two bits of data whose logic values are independent of each other;
at least two bit data buffering means for buffering respective ones of the at least two bits of data from said data input means; and
bit data comparison means for comparing the logic values of the at least two bits of data from the data input means to produce a comparison signal that represents a comparison of the logic values of the at least two bits, and for controlling amounts of current flowing to said at least two bit data buffering means based on the comparison signal.

### Claim 2 (depends on 1)

The buffer of claim 1, wherein said bit data comparison means constitutes:
means for reducing the amounts of current flowing to said at least two bit data buffering means when the at least two bits of data from said data input means have a same logic value.

### Claim 3 (depends on 1)

The buffer of claim 1, wherein said bit data comparison means includes:
means for performing an exclusive-OR operation with respect to the at least two bits of data from said data input means.

### Claim 4 (depends on 1)

The buffer of claim 1, wherein each of said at least two bit data buffering means includes:
a first pull-up driver, connected between a first voltage source and an output line, for transferring a high voltage from said first voltage source to said output line according to the logic value of a corresponding bit of data;
a first pull-down driver, connected between a second voltage source and said output line, said first pull-down driver being driven complementarily to said first pull-up driver, to transfer a low voltage from said second voltage source to said output line according to the logic value of the corresponding bit of data;
a second pull-up driver, connected between said first voltage source and said output line, for transferring the high voltage from said first voltage source to said output line, according to the logic value of the corresponding bit of data;
a second pull-down driver, connected between said second voltage source and said output line, said second pull-down driver being driven complementarily to said second pull-up driver, to transfer the low voltage from said second voltage source to said output line according to the logic value of the corresponding bit of data; and
switching means for switching the corresponding bit of data to said second pull-up driver and said second pull-down driver according to a logic value of the comparison signal from said bit data comparison means.