# US 5,703,811 A · Data output buffer circuit of semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,703,811 A - Document ID: US5703811A - Status: Granted - Kind: A - Application number: 08/580,546 - Filed: 1995-12-29 - Granted: 1997-12-30 - Earliest claimed: 1994-12-29 - Assignees: Samsung Electronocs Co., Ltd. - Inventors: Seung-Moon Yoo; Jei-Hwon Yoo - Web page: https://patentgrep.com/patent/US5703811A ## CPC - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - H03K 19/00315: {in field-effect transistor circuits} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A voltage detection unit between a data output buffer terminal and the gate a transistor which is used to dissipate a high level voltage on the internal data line. The detection unit thus prevents an undesired electrical path from existing in the data output buffer circuit. In one embodiment, the detection unit consists of an NMOS and PMOS transistor connected in series and having a shared node connected to the voltage dissipating transistor. In another embodiment, there is also connected an invertor between the shared node and the gates of the NMOS and PMOS transistors. ## Claims ### Claim 1 A data output buffer circuit of a semiconductor memory device which shares data input/output lines with other semiconductor memory devices, said circuit comprising: a first input node which receives an output data signal; a second input node which receives an inverted output data signal; an output node for outputting a buffer output data signal having an output voltage, said buffer output data signal derived from said output data signal and said inverted output data signal; a pull-up circuit connected between a first voltage and said output node, said pull-up circuit being controlled by said output data signal; a pull-down circuit connected between said output node and a second voltage, said pull-down circuit being controlled by said inverted output data signal; a voltage detection circuit connected between said first voltage and said output node, said voltage detection circuit inputting said buffer output data signal, detecting an output voltage level of said output voltage, and producing a detected voltage signal; and a switch circuit connected between said first input node and said second voltage, said switch circuit including a switch input which receives said detected voltage signal. ### Claim 2 (depends on 1) The data output buffer circuit according to claim 1, wherein said voltage detection circuit comprises: a first MOS transistor connected between said first voltage and said switch input, said first MOS transistor including a first gate electrode; a second MOS transistor connected between said switch input and said output node, said second MOS transistor including a second gate electrode; and a control circuit having a control input connected to said switch input and a control output connected to said first and second gate electrodes, said control circuit generating a control output signal at said control output, said control output signal having a control output voltage level that controls said first and second MOS transistors and which is dependent on said output voltage level detected by said voltage detection circuit. ### Claim 3 (depends on 1) The data output buffer circuit according to claim 1 wherein said switch circuit includes first and second transistors serially connected between said first input node and said second voltage, said first transistor having a first gate electrode connected to said switch input and said second transistor having a second gate electrode connected to an output control signal. ### Claim 4 (depends on 2) The data output buffer circuit according to claim 2 wherein said switch circuit includes first and second transistors serially connected between said first input node and said second voltage, said first transistor having a first gate electrode connected to said switch input and said second transistor having a second gate electrode connected to an output control signal. ### Claim 5 (depends on 2) The data output buffer circuit according to claim 2, wherein: said pull-up circuit comprises a pull-up transistor having a pull-up gate electrode controlled by said output data signal; said pull-down circuit comprises a pull-down transistor having a pull-down gate electrode controlled by said inverted output data signal; and said first voltage is a power supply voltage and said second voltage is a ground potential. ### Claim 6 (depends on 4) The data output buffer circuit according to claim 4, wherein: said pull-up circuit comprises a pull-up transistor having a pull-up gate electrode controlled by said output data signal; said pull-down circuit comprises a pull-down transistor having a pull-down gate electrode controlled by said inverted output data signal; and said first voltage is a power supply voltage and said second voltage is a ground potential. ### Claim 7 (depends on 2) The data output buffer circuit according to claim 2, wherein said first MOS transistor is a PMOS transistor, said second MOS transistor is an NMOS transistor and said control circuit includes an inverter having a trip point that sets a predetermined voltage that will cause a change in logic state of said control output signal. ### Claim 8 (depends on 5) The data output buffer circuit according to claim 5, wherein said first MOS transistor is a PMOS transistor, said second MOS transistor is an NMOS transistor and said control circuit includes an inverter having a trip point that sets a predetermined voltage that will cause a change in logic state of said control output signal. ### Claim 9 (depends on 6) The data output buffer circuit according to claim 6, wherein said first MOS transistor is a PMOS transistor, said second MOS transistor is an NMOS transistor and said control circuit includes an inverter having a trip point that sets a predetermined voltage that will cause a change in logic state of said control output signal. ### Claim 10 (depends on 1) The data output buffer circuit according to claim 1, wherein said voltage detection circuit comprises: a first MOS transistor connected between said first voltage and said switch input, said first MOS transistor including a first gate electrode connected to said second voltage; and a second MOS transistor connected between said switch input and said output node, said second MOS transistor including a second gate electrode connected to said second voltage. ### Claim 11 (depends on 10) The data output buffer circuit according to claim 10 wherein said first MOS transistor is a PMOS transistor and said second MOS transistor is an NMOS transistor. ### Claim 12 A data output buffer circuit of a semiconductor memory device which shares data input/output lines with other semiconductor memory devices, said circuit comprising: a first input node which receives an output data signal; a second input node which receives an inverted output data signal; an output node for outputting a buffer output data signal having an output voltage, said buffer output data signal derived from said output data signal and said inverted output data signal; a pull-up circuit connected between a first voltage and said output node, said pull-up circuit being controlled by said output data signal; a pull-down circuit connected between said output node and a second voltage, said pull-down circuit being controlled by said inverted output data signal; a first switch circuit connected between said first input node and said output node, said first switch circuit being controlled by a third voltage; a voltage detection circuit connected between said first voltage and said output node, said voltage detection circuit inputting said buffer output data signal, detecting an output voltage level of said output voltage, and producing a detected voltage signal, said voltage detection circuit including: a first MOS transistor connected between said first voltage and a switch input, said first MOS transistor including a first gate electrode; a second MOS transistor connected between said switch input and said output node, said second MOS transistor including a second gate electrode; and an inverter having a control input and a control output, said control output connected to said first and second gate electrodes, said inverter generating a control output signal at said control output, said control output signal having a control output voltage level that controls said first and second MOS transistors and which is dependent on a trip point that sets a predetermined voltage that will cause a change in logic state of said control output signal; and a second switch circuit connected between said first input node and said second voltage, said second switch circuit being connected to said switch input and to said control input of said voltage detector circuit. ### Claim 13 (depends on 12) The data output buffer circuit according to claim 12 wherein said voltage detection circuit controls an electrical current path of said pull-up circuit using said first and second switch circuits when a negative voltage exists on said output node and using said first switch circuit when a voltage exists on said output node that is higher than said third voltage. ### Claim 14 (depends on 13) The data output buffer circuit according to claim 13 further including a third switch circuit connected between said second input node and said second voltage, said third switch circuit being controlled by an output control signal. ### Claim 15 (depends on 13) The data output buffer circuit according to claim 13, wherein: said pull-up circuit comprises a pull-up transistor having a pull-up gate electrode controlled by said output data signal; said pull-down circuit comprises a pull-down transistor having a pull-down gate electrode controlled by said inverted output data signal; and said first voltage is a power supply voltage and said second voltage is a ground potential. ### Claim 16 (depends on 14) The data output buffer circuit according to claim 14, wherein each of said first, second and third switching circuits comprise at least one NMOS transistor. ### Claim 17 A data output buffer circuit of a semiconductor memory device which shares data input/output lines with other semiconductor memory devices, said circuit comprising: a first input node which receives an output data signal; a second input node which receives an inverted output data signal; an output node for outputting a buffer output data signal having an output voltage, said buffer output data signal derived from said output data signal and said inverted output data signal; a pull-up circuit connected between a first voltage and said output node, said pull-up circuit being controlled by said output data signal; a pull-down circuit connected between said output node and a second voltage, said pull-down circuit being controlled by said inverted output data signal; a first switch circuit connected between said first input node and said output node, said first switch circuit being controlled by a third voltage; a voltage detection circuit connected between said first voltage and said output node, said voltage detection circuit inputting said buffer output data signal, detecting an output voltage level of said output voltage, and producing a detected voltage signal, said voltage detection circuit including: a first MOS transistor connected between said first voltage and a switch input, said first MOS transistor including a first gate electrode connected to said third voltage; and a second MOS transistor connected between said switch input and said output node, said second MOS transistor including a second gate electrode connected to said third voltage; and a second switch circuit connected between said first input node and said second voltage, said second switch circuit being connected to said switch input of said voltage detection circuit. ### Claim 18 (depends on 17) The data output buffer circuit according to claim 17 wherein said voltage detection circuit controls an electrical current path of said pull-up circuit using said first and second switch circuits when a negative voltage exists on said output node and using said first switch circuit when a voltage exists on said output node that is higher than said third voltage. ### Claim 19 (depends on 18) The data output buffer circuit according to claim 18 further including a third switch circuit connected between said second input node and said second voltage, said third switch circuit being controlled by an output control signal. ### Claim 20 (depends on 19) The data output buffer circuit according to claim 19, wherein: said pull-up circuit comprises a pull-up transistor having a pull-up gate electrode controlled by said output data signal; said pull-down circuit comprises a pull-down transistor having a pull-down gate electrode controlled by said inverted output data signal; and said first voltage is a power supply voltage and said second voltage is a ground potential. ### Claim 21 (depends on 20) The data output buffer circuit according to claim 20, wherein each of said first, second and third switching circuits comprise at least one NMOS transistor. ### Claim 22 (depends on 17) The data output buffer circuit according to claim 17, wherein said third voltage is a ground potential level. ### Claim 23 (depends on 17) The data output buffer circuit according to claim 17, wherein said third voltage is an arbitrary reference voltage level.