# US 5,703,808 A · Non-volatile memory cell and method of programming

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- Number: US 5,703,808 A
- Document ID: US5703808A
- Status: Granted
- Kind: A
- Application number: 08/604,321
- Filed: 1996-02-21
- Granted: 1997-12-30
- Earliest claimed: 1996-02-21
- Assignees: Motorola, Inc.
- Inventors: Jitendra J. Makwana; Darryl F. Monteilh; Effiong A. Omon
- Web page: https://patentgrep.com/patent/US5703808A

## CPC

- H10D 30/685: {from the channel}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The programming time of a non-volatile memory cell (13) is reduced by forming the non-volatile memory cell (13) in a well region (12). The presence of the well region (12) increases the number of electrons that are present in a channel region (14) of the non-volatile memory cell (13). The number of electrons in the channel region (14) is also increased by placing a voltage potential on the well region (12) relative to a source region (15). The voltage differential will inject electrons into the well region (12), which increases the number of electrons in the channel region (14).

## Claims

### Claim 1

A method for programming a non-volatile memory cell, the method comprising the steps of:
providing a non-volatile memory cell, the non-volatile memory cell comprising:
a) a semiconductor substrate of a first conductivity, the semiconductor substrate having a well region of a second conductivity;
b) a contact to the well region to provide a voltage potential between the well region and the semiconductor substrate; and
c) wherein the non-volatile memory cell has a floating gate region, a control gate region, and a dielectric layer overlying the well region, and the non-volatile memory cell having a source region, a drain region, and a channel region in the well region, the channel region being between the source region and the drain region;
placing a first voltage potential on the drain region of the non-volatile memory cell;
placing a second voltage potential on the source region of the non-volatile memory cell, so that the first voltage potential and the second voltage potential provide a current passing through the channel region of the non-volatile memory cell;
placing a third voltage potential on the contact to the well region to provide a flow of electrons into the well region from the source region; and
placing a fourth voltage potential on the control gate region of the non-volatile memory cell, the fourth voltage potential directing electrons from the channel region into the floating gate region by hot carrier injection.

### Claim 2 (depends on 1)

The method for programming the non-volatile memory cell of claim 1 wherein the dielectric layer of the non-volatile memory cell is greater than 300 angstroms thick.

### Claim 3 (depends on 1)

The method for programming the non-volatile memory cell of claim 1 further comprising the step of placing a fifth voltage potential on the semiconductor substrate.

### Claim 4 (depends on 1)

The method for programming the non-volatile memory cell of claim 1 wherein the non-volatile memory cell is an electrically programmable read only memory.

### Claim 5 (depends on 1)

The method for programming the non-volatile memory cell of claim 1 wherein the second voltage potential is a ground potential.

### Claim 6 (depends on 1)

The method for programming the non-volatile memory cell of claim 1 wherein the second voltage potential is placed on both the semiconductor substrate and the source region.

### Claim 7 (depends on 1)

The method for programming the non-volatile memory cell of claim 1 wherein the fourth voltage potential on the control gate region also directs at least some electrons from the flow of electrons provided by the third voltage potential.

### Claim 8 (depends on 1)

The method for programming the non-volatile memory cell of claim 1 wherein the third voltage potential is greater than the second voltage potential and less than the first voltage potential.

### Claim 9 (depends on 1)

The method for programming the non-volatile memory cell of claim 1 wherein the non-volatile memory cell is an electrically erasable and programmable read only memory.

### Claim 10 (depends on 9)

The method for programming the non-volatile memory cell of claim 9 wherein the non-volatile memory cell is a flash electrically erasable and programmable read only memory.

### Claim 11 (depends on 9)

The method for programming the non-volatile memory cell of claim 9 wherein the non-volatile memory cell is a flash electrically programmable read only memory.

### Claim 12 (depends on 1)

The method for programming the non-volatile memory cell of claim 1 wherein the step of providing the non-volatile memory cell includes providing a semiconductor substrate that is of p-type conductivity.

### Claim 13

A method for programming a non-volatile memory cell comprising the steps of:
providing an electrically programmable read only memory cell comprising:
a semiconductor substrate having a well region;
a source region and a drain region formed in the well region; and
a control gate region, a floating gate region, and a dielectric layer overlying the well region, wherein the dielectric layer is at least 300 angstroms thick;
placing a first voltage potential on the drain region of the electrically programmable read only memory cell;
placing a second voltage potential on the source region of the electrically programmable read only memory cell;
placing a third voltage potential on the well region, wherein the third voltage potential is less than the first voltage potential and the third voltage potential is greater than the second voltage potential; and
programming the electrically programmable read only memory cell by placing a fourth voltage potential on the control gate region of the electrically programmable read only memory cell, the fourth voltage potential directing electrons into the floating gate region.

### Claim 14 (depends on 13)

The method for programming the non-volatile memory cell of claim 13 wherein the semiconductor substrate is at a voltage potential different from the third voltage potential.

### Claim 15 (depends on 13)

The method for programming the non-volatile memory cell of claim 13 wherein the second voltage potential is placed on the semiconductor substrate as well as the source region.

### Claim 16 (depends on 13)

The method for programming the non-volatile memory cell of claim 13 wherein the third voltage potential supplies electrons to the well region, at least a portion of the electrons being used to program the electrically programmable read only memory cell.

### Claim 17 (depends on 13)

The method for programming the non-volatile memory cell of claim 13 wherein the third voltage potential is greater than the second voltage potential by at least 1 volt.

### Claim 18 (depends on 13)

The method for programming the non-volatile memory cell of claim 13 wherein the third voltage potential is less than the first voltage potential by at least 1 volt.

### Claim 19 (depends on 13)

The method for programing the non-volatile memory cell of claim 13 wherein the electrically programmable read only memory cell is an electrically erasable and programmable read only memory.

### Claim 20 (depends on 19)

The method for programing the non-volatile memory cell of claim 19 wherein the electrically programmable read only memory cell is a flash electrically erasable and programmable read only memory.

### Claim 21 (depends on 13)

The method for programming the non-volatile memory cell of claim 13 wherein the first voltage potential and the third voltage potential are each between about 1 volt to 25 volts.

### Claim 22 (depends on 13)

The method for programming the non-volatile memory cell of claim 13 wherein the electrically programmable read only memory cell is programmed by hot carrier injection.

### Claim 23

A non-volatile memory cell comprising:
a semiconductor substrate having a surface;
a well region in the semiconductor substrate, the well region contiguous with the surface of the semiconductor substrate;
a source region and a drain region in the well region;
a first dielectric layer overlying the surface of the semiconductor substrate, the first dielectric layer being at least 300 angstroms thick;
a floating gate region overlying the first dielectric layer so that the floating gate region modulates a channel between the source region and the drain region;
a first electrical contact to the semiconductor substrate;
a second electrical contact to the well region; and
wherein the first electrical contact and the second electrical contact are electrically isolated such that a first voltage potential can be placed on the well region while a second voltage potential can be placed on the semiconductor substrate.

### Claim 24 (depends on 23)

The non-volatile memory cell of claim 23 wherein the well region is of a first conductivity, and the source region, the drain region, and the semiconductor substrate are of a second conductivity.

### Claim 25 (depends on 23)

The non-volatile memory cell of claim 23 further comprising:
a second dielectric layer overlying the floating gate region;
a control gate region overlying the second dielectric layer; and
wherein the non-volatile memory cell is an electrically erasable and programmable read only memory.

### Claim 26 (depends on 25)

The non-volatile memory cell of claim 25 wherein the electrically erasable and programmable read only memory is a flash electrically erasable and programmable read only memory.

### Claim 27 (depends on 23)

The non-volatile memory cell of claim 23 wherein the semiconductor substrate is of p-type conductivity.

### Claim 28

A non-volatile memory cell comprising:
a body of semiconductor material;
a well region formed in the body of semiconductor material;
a source region and a drain region in the well region, the source region being of a different conductivity than the well region;
a first dielectric layer overlying the body of semiconductor material, wherein the first dielectric layer covers at least a portion of the well region between the source region and the drain region, the first dielectric layer being at least 350 angstroms thick;
a floating gate region overlying the first dielectric layer;
a first electrical contact to the body of semiconductor material; and
a second electrical contact to the well region, the second electrical contact being electrically isolated from the first electrical contact.

### Claim 29 (depends on 28)

The non-volatile memory cell of claim 28 further comprising:
a second dielectric layer overlying the floating gate region;
a control gate region overlying the second dielectric layer; and
wherein the non-volatile memory cell is an electrically erasable and programmable read only memory.

### Claim 30 (depends on 29)

The non-volatile memory cell of claim 29 wherein the electrically erasable and programmable read only memory is a flash electrically erasable and programmable read only memory.

### Claim 31 (depends on 28)

The non-volatile memory cell of claim 28 wherein the body of semiconductor material is of p-type conductivity.