# US 5,703,803 A · Dynamically controlled, cross-stacked CAM cell

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- Number: US 5,703,803 A
- Document ID: US5703803A
- Status: Granted
- Kind: A
- Application number: 08/639,556
- Filed: 1996-04-29
- Granted: 1997-12-30
- Earliest claimed: 1996-04-29
- Assignees: Intel Corporation
- Inventors: Victor Shadan; Anurag Nigam
- Web page: https://patentgrep.com/patent/US5703803A

## CPC

- G11C 15/04: using semiconductor elements
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory cell comprising a storage cell and a comparison circuit. The storage cell has a second node and a third node. The comparison circuit is coupled to the storage cell and comprises a first plurality of transistors coupled in series to a first input and a second plurality of transistors coupled in series to a second input and coupled to the first plurality of transistors by a first node and by a source voltage node. A match line coupled to the first node indicates a miss when values on the first and second inputs are different than values stored in the storage cell.

## Claims

### Claim 1

An apparatus that stores a bit in a content addressable memory, comprising:
a storage cell comprising:
a second node that stores an inverse of an address bit;
a third node that stores the address bit;
a read/write input that enables the address bit and the inverse of the address bit to be stored in the storage cell;
a comparison circuit coupled to the storage cell through the second and third nodes, comprising:
a first transistor of a first type having a source coupled to a source voltage node and a gate coupled to the second node;
a second transistor of the first type having a source coupled to a drain of the first transistor, a gate coupled to a first input that carries a virtual address bit, and a drain coupled to a first node;
a third transistor of the first type having a source coupled to the source voltage node and a gate coupled to the third node;
a fourth transistor of the first type having a source coupled to a drain of the third transistor, a gate coupled to a second input that carries an inverse of the virtual address bit, and a drain coupled to the first node;
a match indication line coupled to the first node that indicates a miss when values on the first and second inputs do not match values stored in the storage cell.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising a fifth transistor of the second type having a gate coupled to the first node, a drain coupled to a ground potential, and a source coupled to the match indication line.

### Claim 3 (depends on 2)

The apparatus of claim 2, further comprising a sixth transistor of the second type having a source coupled to the first node, a gate coupled to a clock line, and a drain coupled to the ground potential, the fifth transistor causing the match indication line to change value when a miss is indicated and the clock line has a high value.

### Claim 4 (depends on 2)

The apparatus of claim 2, further comprising a sixth transistor of the second type having a source coupled to the first node and a gate coupled to the second input.

### Claim 5 (depends on 4)

The apparatus of claim 4, further comprising a seventh transistor of the second type having a source coupled to the drain of the sixth transistor, a drain coupled to the ground potential, and a gate coupled to the first input.