# US 5,703,801 A · Logarithm/inverse-logarithm converter utilizing second-order term and method of using same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 5,703,801 A
- Document ID: US5703801A
- Status: Granted
- Kind: A
- Application number: 08/382,467
- Filed: 1995-01-31
- Granted: 1997-12-30
- Earliest claimed: 1995-01-31
- Assignees: Motorola, Inc.
- Inventors: ShaoWei Pan; Shay-Ping Thomas Wang
- Web page: https://patentgrep.com/patent/US5703801A

## CPC

- G06F 1/0356: {by using two or more smaller tables, e.g. addressed by parts of the argument}
- H03M 7/50: Conversion to or from non-linear codes, e.g. companding
- G06F 2101/10: Logarithmic or exponential functions
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, a multiplier, and two adders. The memory stores a plurality of parameters and second-order terms which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of computing the parameters and second-order terms is also disclosed.

## Claims

### Claim 1

A logarithm converter, which comprises:
a memory for storing a plurality of parameters and a plurality of second-order terms, wherein the parameters are calculated using a least squares method to estimate a logarithmic function over a domain of input values, the memory providing as output ones of the parameters and a second-order term which correspond to an input value; and
arithmetic means, operatively coupled to the memory, for generating a log value by performing arithmetic operations on the input value, the ones of the parameters, and the second-order term.

### Claim 2 (depends on 1)

The logarithm converter of claim 1, wherein the logarithmic function is estimated with a second-order polynomial.

### Claim 3 (depends on 2)

The logarithm converter of claim 2, wherein the ones of the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:
a multiplier for multiplying the first-order parameter by the input value to produce a proportional term;
a first adder for summing the proportional term and the second-order term to produce a first sum; and
a second adder for summing the first sum and the zero-order parameter to produce the log value.

### Claim 4 (depends on 2)

The logarithm converter of claim 2, wherein the ones of the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:
a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;
a first adder for summing the proportional term and the second-order term to produce a first sum; and
a second adder for summing the first sum and the zero-order parameter to produce the log value.

### Claim 5 (depends on 1)

The logarithm converter of claim 1, wherein the input value is a binary value having a plurality of bits used to retrieve from the memory the ones of the plurality of parameters and the second-order term.

### Claim 6 (depends on 1)

The logarithm converter of claim 1, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.

### Claim 7

A logarithm converter for generating a log value corresponding to an input value, the logarithm converter comprising:
a memory for storing a plurality of second-order terms and a plurality of parameter pairs, wherein each of the parameter pairs is calculated using a least squares method to estimate a logarithmic function over an interval of input values, the memory providing as output a parameter pair and a second-order term which correspond to the input value, wherein the parameter pair has a zero-order parameter and a first-order parameter;
a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;
a first adder for summing the proportional term and the second-order term to produce a first sum; and
a second adder for summing the first sum and the zero-order parameter to produce the log value.

### Claim 8 (depends on 7)

The logarithm converter of claim 7, wherein the input value is a binary value having a plurality of bits used to retrieve the parameter pair from the memory.

### Claim 9 (depends on 7)

The logarithm converter of claim 7, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.

### Claim 10 (depends on 7)

The logarithm converter of claim 7, wherein the logarithmic function is estimated with a second order polynomial.

### Claim 11

A computing device, which comprises:
a processing unit for executing a computer operation which utilizes a log value;
a computer memory for storing a computer program which includes the computer operation;
a bus for connecting the processing unit and the computer memory; and
a logarithm converter which receives an input value and includes:
a memory for storing a plurality of parameters and a plurality of second-order terms, wherein the parameters are calculated using a least squares method to estimate a logarithmic function over a domain of input values, the memory providing as output ones of the parameters and a second-order term which correspond to the input value; and
arithmetic means, operatively coupled to the memory, for generating the log value by performing arithmetic operations on the input value, the ones of the parameters, and the second-order term.

### Claim 12 (depends on 11)

The computing device of claim 11, wherein the logarithmic function is estimated with a second-order polynomial.

### Claim 13 (depends on 11)

The computing device of claim 11, wherein the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:
a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;
a first adder for summing the proportional term and the second-order term to produce a first sum; and
a second adder for summing the first sum and the zero-order parameter to produce the log value.

### Claim 14 (depends on 11)

The computing device of claim 11, wherein the input value is a binary value having a plurality of bits used to retrieve from the memory the ones of the plurality of parameters.

### Claim 15 (depends on 11)

The logarithm converter of claim 11, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.

### Claim 16

An inverse-logarithm converter, which comprises:
a memory for storing a plurality of parameters and a plurality of second-order terms, wherein the parameters are calculated using a least squares method to estimate an inverse-logarithmic function over a domain of input values, the memory providing as output ones of the parameters and a second-order term which correspond to an input value; and
arithmetic means, operatively coupled to the memory, for generating an inverse-log value by performing arithmetic operations on the input value, the ones of the parameters, and the second-order term.

### Claim 17 (depends on 16)

The inverse-logarithm converter of claim 16, wherein the inverse-logarithmic function is estimated with a second-order polynomial.

### Claim 18 (depends on 17)

The inverse-logarithm converter of claim 17, wherein the ones of the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:
a multiplier for multiplying the first-order parameter by the input value to produce a proportional term;
a first adder for summing the proportional term and the second-order term to produce a first sum; and
a second adder for summing the first sum and the zero-order parameter to produce the inverse-log value.

### Claim 19 (depends on 17)

The inverse-logarithm converter of claim 17, wherein the ones of the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:
a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;
a first adder for summing the proportional term and the second-order term to produce a first sum; and
a second adder for summing the first sum and the zero-order parameter to produce the inverse-log value.

### Claim 20 (depends on 16)

The inverse-logarithm converter of claim 16, wherein the input value is a binary value having a plurality of bits used to retrieve from the memory the ones of the plurality of parameters and the second-order term.

### Claim 21 (depends on 16)

The inverse-logarithm converter of claim 16, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.

### Claim 22

An inverse-logarithm converter for generating an inverse-log value corresponding to an input value, the inverse-logarithm converter comprising:
a memory for storing a plurality of second-order terms and a plurality of parameter pairs, wherein each of the parameter pairs is calculated using a least squares method to estimate an inverse-logarithmic function over an interval of input values, the memory providing as output a parameter pair and a second-order term which correspond to the input value, wherein the parameter pair has a zero-order parameter and a first-order parameter;
a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;
a first adder for summing the proportional term and the second-order term to produce a first sum; and
a second adder for summing the first sum and the zero-order parameter to produce the inverse-log value.

### Claim 23 (depends on 22)

The inverse-logarithm converter of claim 22, wherein the input value is a binary value having a plurality of bits used to retrieve the parameter pair from the memory.

### Claim 24 (depends on 22)

The inverse-logarithm converter of claim 22, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.

### Claim 25 (depends on 22)

The inverse-logarithm converter of claim 22, wherein the inverse-logarithmic function is estimated with a second order polynomial.

### Claim 26

A computing device, which comprises:
a processing unit for executing a computer operation which utilizes an inverse-log value;
a computer memory for storing a computer program which includes the computer operation;
a bus for connecting the processing unit and the computer memory; and
an inverse-logarithm converter which receives an input value and includes:
a memory for storing a plurality of parameters and a plurality of second-order terms, wherein the parameters are calculated using a least squares method to estimate an inverse-logarithmic function over a domain of input values, the memory providing as output ones of the parameters and a second-order term which correspond to the input value; and
arithmetic means, operatively coupled to the memory, for generating the inverse-log value by performing arithmetic operations on the input value, the ones of the parameters, and the second-order term.

### Claim 27 (depends on 16)

The computing device of claim 16, wherein the inverse-logarithmic function is estimated with a second-order polynomial.

### Claim 28 (depends on 27)

The computing device of claim 27, wherein the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:
a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;
a first adder for summing the proportional term and the second-order term to produce a first sum; and
a second adder for summing the first sum and the zero-order parameter to produce the inverse-log value.

### Claim 29 (depends on 26)

The computing device of claim 26, wherein the input value is a binary value having a plurality of bits used to retrieve from the memory the ones of the plurality of parameters.

### Claim 30 (depends on 26)

The inverse-logarithm converter of claim 26, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.