# US 5,703,790 A · Series connection of multiple digital devices to a single power source

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- Number: US 5,703,790 A
- Document ID: US5703790A
- Status: Granted
- Kind: A
- Application number: 08/607,543
- Filed: 1996-02-27
- Granted: 1997-12-30
- Earliest claimed: 1996-02-27
- Assignees: Hughes Electronics Corporation
- Inventors: William D. Farwell
- Web page: https://patentgrep.com/patent/US5703790A

## CPC

- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A digital processing system including a first processor (11) and a second processor (21) connected in series between a first power supply node (101) and a second power supply node (103). The second processor is configured to operate at a variable processing rate, as controlled by the output of a processing rate controller (33) that is responsive to the voltage across the supply terminals of the second processor and a first reference voltage. An auxiliary shunt regulator (39) is connected across the supply terminals of the second processor and is controlled by a regulator controller (37) to prevent the voltage across the supply terminals of the second processor from exceeding a second reference voltage.

## Claims

### Claim 1

A digital processor system connected between a first power supply node and a second power supply node, comprising:
a first processor having a first supply terminal and a second supply terminal, said first supply terminal of said first processor being connected to the first supply node;
a second processor having a first supply terminal and a second supply terminal, said first supply terminal of said second processor being connected to said second supply terminal of said first processor at an intermediate supply node and said second supply terminal of said second processor being connected to the second supply node, such that said first processor and said second processor are connected in series between the first supply node and the second supply node; and
processing rate control means responsive to a predetermined reference voltage and a voltage at said intermediate supply node for controlling a processing rate of said second processor to maintain said voltage at said intermediate supply node close to said predetermined reference voltage.

### Claim 2 (depends on 1)

The digital processor system of claim 1 wherein said processing rate control means includes a subtraction circuit responsive to the predetermined reference voltage and the voltage at said intermediate supply node.

### Claim 3 (depends on 2)

The digital processor system of claim 2 wherein said processing rate control means further includes means for providing a variable clock frequency to said second processor.

### Claim 4 (depends on 2)

The digital processor system of claim 2 wherein said processing rate control means further includes means for providing an interrupt signal to said second processor.

### Claim 5 (depends on 1)

The digital processor system of claim 1 further including:
regulator control means responsive to the voltage at said intermediate supply node and a regulator reference voltage for providing a regulator control signal; and
a shunt regulator responsive to said regulator control means and connected between said intermediate supply node and the second supply node, said shunt regulator preventing the voltage at said intermediate node from exceeding said regulator reference voltage.

### Claim 6 (depends on 5)

The digital processor of claim 5 wherein said regulator control means includes a subtraction circuit responsive to the voltage at said intermediate supply node and a regulator reference voltage.