# US 5,703,656 A · Digital phase error detector for locking to color subcarrier of video signals > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,703,656 A - Document ID: US5703656A - Status: Granted - Kind: A - Application number: 08/571,018 - Filed: 1995-12-12 - Granted: 1997-12-30 - Earliest claimed: 1995-12-12 - Assignees: TRW Inc. - Inventors: Gregory A. Shreve; Kim S. Guzzino; Robert W. Hulvey - Web page: https://patentgrep.com/patent/US5703656A ## CPC - H04N 9/45: Generation or recovery of colour sub-carriers - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A digital phase error detector for locking to a color subcarrier signal in an analog video signal. The digital phase error detector includes a digitizer responsive to a sample clock which generates a first digital data stream from the analog video signal. Filtering circuitry filters the first digital data stream to generate a second data stream by substantially eliminating DC offset of the color subcarrier signal digitized by the digitizer. A mixer mixes the second digital data stream to generate a third digital data stream representing sum and difference frequencies of a product of the color subcarrier signal and a reference clock. An accumulator accumulates this product which represents a phase error between the color subcarrier signal and the reference clock. A voltage controlled oscillator is responsive to this phase error for generating the sample clock. ## Claims ### Claim 1 A digital phase error detector for locking to a color subcarrier signal in an analog video signal, said digital phase error detector comprising: digitizing means for digitizing said color subcarrier signal in said analog video signal to generate a first digital data stream, said digitizing means being responsive to a sample clock signal; filtering means for generating a second digital data stream by filtering said first digital data stream to substantially eliminate DC offset of said color subcarrier signal digitized by said digitizing means; mixing means for generating a third digital data stream from said second digital data stream representing sum and difference frequencies of a product of said color subcarrier signal and a reference clock signal; accumulator means for accumulating said product of said third digital data stream, said accumulated product representing a phase error between said color subcarrier signal and said reference clock signal which is substantially free of DC offset of said color subcarrier signal; and a voltage controlled oscillator responsive to said phase error for generating said sample clock signal. ### Claim 2 (depends on 1) The digital phase error detector as defined in claim 1 wherein said digitizing means includes an analog-to-digital converter, said analog-to-digital converter receives said color subcarrier signal in said analog video signal and digitizes said color subcarrier signal in response to the sample clock signal to generate said first digital data stream. ### Claim 3 (depends on 1) The digital phase error detector as defined in claim 1 wherein said filtering means includes an adder for receiving an inverted first digital data stream and said first digital data stream 180.degree. out of phase with the inverted first digital data stream to substantially eliminate the DC offset of said color digitizer signal digitized by the digitizing means. ### Claim 4 (depends on 3) The digital phase error detector as defined in claim 3 wherein said filtering means further includes a first digital register and a second digital register for delaying said first digital data stream 180.degree. and an inverter for inverting said first digital data stream to generate said inverted first digital data stream. ### Claim 5 (depends on 4) The digital phase error detector as defined in claim 4 wherein said filtering means is responsive to said sample clock signal. ### Claim 6 (depends on 1) The digital phase error detector as defined in claim 1 wherein said mixing means includes a multiplexer for receiving said second digital data stream from said filtering means, said multiplexer being responsive to said reference clock signal. ### Claim 7 (depends on 6) The digital phase error detector as defined in claim 6 wherein said multiplexer includes a first input and a second input, said first input receiving said second digital data stream and said second input receiving an inverted second digital data stream. ### Claim 8 (depends on 1) The digital phase error detector as defined in claim 1 wherein said accumulator means includes a digital register operable to accumulate said product while said color subcarrier signal is active. ### Claim 9 (depends on 8) The digital phase error detector as defined in claim 8 wherein said accumulator means further includes an adder having a feedback input. ### Claim 10 (depends on 1) The digital phase error detector as defined in claim 1 further comprising an error latch means for latching said accumulated product from said accumulator means. ### Claim 11 (depends on 1) The digital phase error detector as defined in claim 1 further comprising phase error means for converting said accumulated product representing said phase error to a control voltage to control said voltage controlled oscillator. ### Claim 12 (depends on 11) The digital phase error detector as defined in claim 11 wherein said phase error means includes an accumulator and a loop filter for generating said control voltage. ### Claim 13 (depends on 12) The digital phase error detector as defined in claim 12 wherein said accumulator generates a continuous pulse width modulated (PWM) output which is updated as each color subcarrier signal is digitized. ### Claim 14 (depends on 1) The digital phase error detector as defined in claim 1 further comprising a divide by four circuit for generating said reference clock signal from said voltage controlled oscillator. ### Claim 15 (depends on 1) The digital phase error detector as defined in claim 1 wherein said sample clock signal has a frequency of about four times the frequency of said reference clock signal. ### Claim 16 (depends on 15) The digital phase error detector as defined in claim 15 wherein said reference clock signal has a frequency substantially the same as said color subcarrier signal. ### Claim 17 (depends on 1) The digital phase error detector as defined in claim 1 wherein said analog video signal has a format selected from the group consisting of NTSC (National Television System Committee), PAL (Phase Alternation by Line) and SECAM (Sequence a Memoire). ### Claim 18 A digital phase error detector for locking to a color subcarrier signal in an analog video signal, said digital phase error detector comprising: a digitizer, said digitizer being responsive to a sample clock signal and operable to digitize said color subcarrier signal to generate a first digital data stream from said analog video signal; a bandpass filter, said bandpass filter operable to generate a second digital data stream by filtering said first digital data stream to substantially eliminate DC offset of said color subcarrier signal digitized by said digitizer; a mixer, said mixer operable to generate a third digital data stream from said second digital data stream representing sum and difference frequencies of a product of said color subcarrier signal and a reference clock signal; an accumulator, said accumulator operable to accumulate said product of said third digital data stream representing a phase error between said color subcarrier signal and said reference clock signal which is substantially free of DC offset of said color subcarrier signal; phase error circuitry, said phase error circuitry operable to convert said phase error to a control voltage; and a voltage controlled oscillator responsive to said control voltage for generating said sample clock signal. ### Claim 19 (depends on 18) A digital phase error detector as defined in claim 18 wherein said bandpass filter includes a first digital register and a second digital register for delaying said first digital data stream 180.degree. out of phase with an inverted first digital data stream, an inverter for inverting said first digital data stream to generate said inverted first digital data stream, and an adder for receiving said inverted first digital data stream and said first digital data stream 180.degree. out of phase with said inverted first digital data stream to substantially eliminate the DC offset of said color subcarrier signal digitized by the digitizer. ### Claim 20 (depends on 18) The digital phase error detector as defined in claim 18 wherein said phase error circuitry includes an accumulator and a loop filter for generating said control voltage, said accumulator providing a continuous pulse width modulated (PWM) output. ### Claim 21 (depends on 18) The digital phase error detector as defined in claim 18 wherein said sample clock signal has a frequency of about four times the frequency of said reference clock signal and said reference clock signal has a frequency substantially the same as said color subcarrier signal. ### Claim 22 A method for locking to a color subcarrier signal in an analog video signal, said method comprising the steps of: digitizing said color subcarrier signal in said analog video signal to generate a first digital data stream; filtering said first digital data stream to substantially eliminate DC offset of said digitized color subcarrier signal to generate a second digital data stream; mixing said second digital data stream to generate a third digital data stream representing sum and difference frequencies of a product of said color subcarrier signal and a reference clock signal; accumulating said product which is substantially free of DC offset of said color subcarrier signal; converting said product to a control voltage; and controlling a voltage controlled oscillator with said control voltage to generate a sample clock signal. ### Claim 23 (depends on 22) The method as defined in claim 22 wherein the step of filtering said first digital data stream further includes the steps of: generating an inverted first digital data stream; generating a first digital data stream 180.degree. out of phase with said inverted first digital data stream; and adding said inverted first digital data stream with said first digital data stream 180.degree. out of phase with said first inverted digital data stream. ### Claim 24 (depends on 22) The method as defined in claim 22 wherein the step of converting said product to a control voltage further includes the step of generating a continuous pulse width modulated (PWM) output.