# US 5,703,653 A · Video signal compression apparatus for horizontal compression of a video signal

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- Number: US 5,703,653 A
- Document ID: US5703653A
- Status: Granted
- Kind: A
- Application number: 08/725,074
- Filed: 1996-10-02
- Granted: 1997-12-30
- Earliest claimed: 1993-12-22
- Assignees: Matsushita Electric Industrial Co., Ltd.
- Inventors: Yosuke Izawa; Masahiro Tani; Maoji Okumura; Yutaka Nio; Toshichika Sato
- Web page: https://patentgrep.com/patent/US5703653A

## CPC

- H04N 7/0122: {the input and the output signals having different aspect ratios}
- H04N 5/14: Picture signal circuitry for video frequency region (cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00)
- Y10S 348/913: Letterbox, e.g. display 16:9 aspect ratio image on 4:3 screen
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A video signal compression apparatus extracts a specific value written in a read only memory at every system clock pulse. The specific value can be varied at every clock pulse. Therefore, for example, only the center part of a picture can be horizontally compressed. A FIFO memory may be used. It is possible to select a mode with a fixed compression ratio or a mode in which a compression ratio varies at every clock pulse. Further, the fixed compression ratio can be set from the outside. Display position of the picture can also be changed.

## Claims

### Claim 1

A video signal compression apparatus for compressing a video signal comprising:
memory means for storing an input video signal and outputting data value D.sub.n for address A.sub.n and data value D.sub.n+1 for address A.sub.n+1 when a read address A.sub.n is given;
value generator means for counting a number of system clock pulses and outputting a previously written count value corresponding to said number of counted system clock pulses;
signal selector means for selecting one of the count value and a fixed value to generate a selector output value;
register means for storing and outputting a register value;
first adder means for adding the selector output value and the register value to generate an adder output value;
said register means for latching the adder output value, wherein an integer part of the adder output value is said read address A.sub.n ;
subtracter means for subtracting data D.sub.n from data D.sub.n+1 and generating a subtraction value;
multiplier means for multiplying said subtraction value by a decimal part of the register value to generate a multiplier output value; and
second adder means for adding the data value D.sub.n and the multiplier output value to generate said compressed video signal.