# US 5,703,629 A · Computer system including protected graphics display control signal sequencing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,703,629 A - Document ID: US5703629A - Status: Granted - Kind: A - Application number: 08/489,011 - Filed: 1995-06-08 - Granted: 1997-12-30 - Earliest claimed: 1995-06-08 - Assignees: Dell USA, L.P. - Inventors: Lois D. Mermelstein; Kendall C. Witte - Web page: https://patentgrep.com/patent/US5703629A ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G06F 3/147: using display panels - G09G 5/363: {Graphics controllers} - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/046: Dealing with screen burn-in prevention or compensation of the effects thereof - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computer system is provided which assures that display control signals provided to a display are properly sequenced despite the presence of ill-behaved application software. The risk of damage to displays which require control signals to be in a predetermined sequence is thus significantly reduced. An enable signal from the system's graphics controller is intercepted by a microcontroller. The microcontroller generate its own properly sequenced and timed display control signals in response to the enable signal from the graphics controller. The microcontroller controls a switching apparatus which couples clock and data signals from the graphics controller to the display at an appropriate time in the control signal sequence. ## Claims ### Claim 1 An information handling system comprising: a processor; a main memory coupled to the processor; a graphics controller coupled to the processor, the graphics controller supplying clock signals, data signals and an enable signal; a display; a switching apparatus switchably coupling the display to the graphics controller; and a microcontroller coupled to the graphics controller, the switching apparatus and to the display, the microcontroller monitoring for a first transition in the enable signal, the microcontroller generating a first sequence of display control signals to power-up the display when the microcontroller detects the first transition in the enable signal, the microcontroller activating the switching apparatus to a coupling state to permit transmission of the clock signals and data signals from the graphics controller to the display after the microcontroller detects the first transition in the enable signal. ### Claim 2 (depends on 1) The information handling system of claim 1 wherein the microcontroller further generates a second sequence of display control signals to power-down the display when the microcontroller detects a second transition in the enable signal, the microcontroller activating the switching apparatus to decouple the display from the graphics controller after the microcontroller detects the second transition in the enable signal. ### Claim 3 (depends on 1) The information handling system of claim 1 wherein the display is a flat panel display. ### Claim 4 (depends on 1) The information handling system of claim 1 wherein the switching apparatus is a tri-state buffer. ### Claim 5 (depends on 1) The information handling system of claim 1 further comprising: a main power plane for supplying power within the information handling system; a power switch coupled to the microcontroller; said microcontroller further monitoring for switching of the power switch to an off state which signifies that the information handling system is to be powered down, and in response the microcontroller generating a second sequence of display control signals to power down the display and activate the switching apparatus to decouple the display from the graphics controller, said microcontroller subsequently powering down the main power plane. ### Claim 6 A graphics control system for an information handling apparatus which includes a processor and a main memory coupled to the processor, the information handling apparatus further including a display, the graphics control system comprising: a graphics controller for supplying clock signals, data signals and an enable signal; a switching apparatus switchably coupling the graphics controller to the display; and a microcontroller coupled to the graphics controller, the switching apparatus and to the display, the microcontroller monitoring for a first transition in the enable signal, the microcontroller generating a first sequence of display control signals to power-up the display when the microcontroller detects the first transition in the enable signal, the microcontroller activating the switching apparatus to a coupling state to permit transmission of the clock signals and data signals from the graphics controller to the display after the microcontroller detects the first transition in the enable signal. ### Claim 7 (depends on 6) The information handling system of claim 6 wherein the microcontroller further generates a second sequence of display control signals to power-down the display when the microcontroller detects a second transition in the enable signal, the microcontroller activating the switching apparatus to decouple the display from the graphics controller after the microcontroller detects the second transition in the enable signal. ### Claim 8 (depends on 6) The information handling system of claim 6 wherein the display is a flat panel display. ### Claim 9 (depends on 6) The information handling system of claim 6 wherein the switching apparatus is a tri-state buffer. ### Claim 10 An information handling system comprising: a processor; a local bus coupled to the processor; a main memory coupled to the processor; a graphics controller coupled to the local bus, the graphics controller supplying clock signals, data signals and an enable signal; a display; a switching apparatus switchably coupling the display to the graphics controller; and control means, coupled to the graphics controller, the switching apparatus and to the display, the control means monitoring for a first transition in the enable signal, the control means generating a first sequence of display control signals to power-up the display when the control means detects the first transition in the enable signal, the control means activating the switching apparatus to a coupling state to permit transmission of the clock signals and data signals from the graphics controller to the display after the control means detects the first transition in the enable signal. ### Claim 11 (depends on 10) The information handling system of claim 10 wherein the control means further generates a second sequence of display control signals to power-down the display when the control means detects a second transition in the enable signal, the control means activating the switching apparatus to decouple the display from the graphics controller after the control means detects the second transition in the enable signal. ### Claim 12 (depends on 10) The information handling system of claim 10 wherein the display is a flat panel display. ### Claim 13 (depends on 10) The information handling system of claim 10 wherein the switching apparatus is a tri-state buffer. ### Claim 14 A method of controlling a display system for an information handling apparatus, the display system including a graphics controller coupled by a switching apparatus to a display, the display system further including a microcontroller coupled to the graphics controller, the switching apparatus and the display, the method comprising the steps of: the graphics controller generating clock signals, data signals and an enable signal; monitoring, by the microcontroller, for a first transition in the enable signal; generating, by the microcontroller, a first sequence of display control signals to power-up the display when the microcontroller detects the first transition of the enable signal; and activating, by the microcontroller, the switching apparatus to a coupling state to permit transmission of the clock signals and data signals from the graphics controller to the display after the microcontroller detects the first transition of the enable signal. ### Claim 15 (depends on 14) The method of claim 14 further comprising the step of generating, by the microcontroller, a second sequence of display control signals to power-down the display when the microcontroller detects a second transition in the enable signal; and activating, by the microcontroller, the switching apparatus to decouple the display from the graphics controller after the microcontroller detects the second transition in the enable signal. ### Claim 16 (depends on 14) The method of claim 14 wherein the information handling apparatus includes a main power plane coupled to the microcontroller and a power switch coupled to the microcontroller, the method further comprising: monitoring the power switch by the microcontroller to determine when the power switch is switched to an off state which indicates that the information handling apparatus is to be powered down; generating a second sequence of display control signals by the microcontroller to power-down the display and activate the switching apparatus to decouple the display from the graphics controller, said microcontroller subsequently powering down the main power plane.