# US 5,703,608 A · Signal processing circuit

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- Number: US 5,703,608 A
- Document ID: US5703608A
- Status: Granted
- Kind: A
- Application number: 08/538,375
- Filed: 1995-10-03
- Granted: 1997-12-30
- Earliest claimed: 1994-10-04
- Assignees: Rohm Co., Ltd.
- Inventors: Kaeko Kuga
- Web page: https://patentgrep.com/patent/US5703608A

## CPC

- G09G 3/3688: {suitable for active matrices only}
- G09G 3/2011: {by amplitude modulation}
- G09G 3/3614: {Control of polarity reversal in general}
- G09G 2320/0219: Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A signal processor alternately outputs two input signals to a common output terminal every predetermined period to form a single serial signal. A capacitor for holding the input signal is provided on each input signal transmitting path. A buffer is provided at each of the preceding and succeeding stages of each capacitor. The turning on and off of these buffers is controlled by a single switch. The switch is controlled so that when one capacitor is supplied with the input signal, the other capacitor outputs a signal.

## Claims

### Claim 1

A signal processor comprising:
a first input terminal supplied with a first signal;
a second input terminal supplied with a second signal;
first and second input buffers connected to the first and second input terminals, respectively;
a first capacitor connected to an output side of the first input buffer and to a reference potential point for holding the first signal;
a second capacitor connected to an output side of the second input buffer and to the reference potential point for holding the second signal;
a first output buffer connected to the first capacitor;
a second output buffer connected to the second capacitor;
an output terminal supplied with outputs of the first and second output buffers;
a power source for activating the first and second input buffers and the first and second output buffers; and
switch means which alternately repeats a first period during which the first input buffer and the second output buffer are connected to the power source and a second period during which the second input buffer and the first output buffer are connected to the power source.

### Claim 2 (depends on 1)

A signal processor according to claim 1, wherein said first and second input buffers, said first and second output buffers and said switch means are each constituted by a metal oxide semiconductor transistor.

### Claim 3 (depends on 1)

A signal processor according to claim 1, wherein said first and second signals are video signals, and wherein said output terminal is connected to a video display device.

### Claim 4 (depends on 3)

A signal processor according to claim 3, wherein changeover of said switch means is controlled by a pulse for each pixel of the display device.

### Claim 5 (depends on 3)

A signal processor according to claim 3, wherein said video display device is a liquid crystal display device.

### Claim 6 (depends on 1)

A signal processor according to claim 1,
wherein the buffers are composed of a first transistor circuit, and
wherein the switch means is composed of a second transistor circuit and includes a plurality of transistors, each of the plurality of transistors receiving at its gate electrode a switching pulse, being connected at its second electrode to the first transistor circuit, and being connected at its third electrode to the power source.

### Claim 7

A signal processor comprising:
a first input terminal supplied with a first video signal of a first field;
a second input terminal supplied with a second video signal of a second field;
first and second input buffers connected to the first and second input terminals, respectively;
a first capacitor connected to an output side of the first input buffer and to a reference potential point for holding the first signal;
a second capacitor connected to an output side of the second input buffer and to the reference potential point for holding the second signal;
a first output buffer connected to the first capacitor;
a second output buffer connected to the second capacitor;
an output terminal supplied with outputs of the first and second output buffers and supplying the outputs to a liquid crystal display device of a non-interlace type;
a power source for activating the first and second input buffers and the first and second output buffers; and
switch means for alternately connecting 1) the first input buffer and the second output buffer to the power source during a first period and 2) the second input buffer and the first output buffer to the power source during a second period, wherein changeover of said switch means is controlled by a pulse for each pixel of the display device.