# US 5,703,596 A · Demodulating integrator/demultiplexer

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- Number: US 5,703,596 A
- Document ID: US5703596A
- Status: Granted
- Kind: A
- Application number: 08/691,766
- Filed: 1996-08-02
- Granted: 1997-12-30
- Earliest claimed: 1996-08-02
- Assignees: Boeing North American, Inc.
- Inventors: Stanley A. White
- Web page: https://patentgrep.com/patent/US5703596A

## CPC

- G01S 7/288: Coherent receivers
- G01S 7/2886: {using I/Q processing}
- G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES

## Abstract

A radar digital IF (intermediate-frequency) signal is to be complex demodulated, then processed through a two-channel real lowpass filter, prior to Doppler correction, clutter filtering, and other usual processing steps. A particularly efficient form of lowpass filtering for such applications is the so-called CIC (cascaded integrator/comb) filter. The first stage of such a filter is always an integrator. A conventional mechanization would therefore feature a conventional complex demodulator followed by an accumulator on each of the two demodulator outputs, followed by more processing. This invention more efficiently mechanizes this function by replacing the usual pair of multipliers and pair of accumulators (or integrators) with a single two-delay (54, 58) accumulator having an add/subtract control (48) on the input adder (42), and a pair of multiplexer switches (62, 66).

## Claims

### Claim 1

Apparatus for producing a complex-demodulated-and-integrated sampled radar signal from a sampled radar signal, wherein:
(a) the sampled radar signal has been generated by combining a radar signal and a sampling clock signal;
(b) the sampling clock signal has a sampling frequency;
(c) the sampled radar signal has a center frequency equal to a fourth of the sampling frequency, and has a bandwidth less than half the sampling frequency; and
(d) the apparatus comprises:
(1) a counter-control signal generator connected to receive the sampling clock signal, and constructed to produce a first control signal and a second control signal;
(2) a combiner constructed to add the sampled radar signal to a feedback signal when the first control signal is one, and to otherwise subtract the sampled radar signal from the feedback signal, thereby producing a combiner output signal;
(3) a first delay element connected to receive the combiner output signal and constructed to thereby provide a first delayed output signal;
(4) a second delay element connected to receive the first delayed output signal and constructed to thereby provide a second delayed output signal, the second delayed output signal being the feedback signal;
(5) a first multiplexer switch constructed to output the combiner output signal when the second control signal is one and to output the first delayed output signal otherwise, an output signal from the first multiplexer switch being an in-phase component of the complex-demodulated-and-integrated sampled radar signal; and
(6) a second multiplexer switch constructed to output the combiner output signal when the second control signal is zero and to output the first delayed output signal otherwise, an output signal from the second multiplexer switch being a quadrature component of the complex-demodulated-and-integrated sampled radar signal.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first control signal is one when cos ›(.pi./4)(2n+1)!>0 and is zero otherwise, where n is a count of pulses of the sampling clock signal.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the second control signal is one when n is odd and is zero when n is even, where n is a count of pulses of the sampling clock signal.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the second control signal is one when n is odd and is zero when n is even.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the counter is a two-bit four-state device.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the first control signal is an exclusive nor of a counter least-significant-bit (LSB) output and a counter most significant-bit (MSB) output.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the second control signal is a counter least-significant-bit (LSB) output.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the second control signal is a counter least-significant-bit (LSB) output.